The Xilinx CoreGenerator is a tool that allows you to incorporate several kinds of predesigned modules into your final design. If you have Xilinx ISE installed on your Windows system, to open CoreGenerator click:
Start->Xilinx ISE -> Accessories -> Core Generator System.When the Core Generator software opens, a prompt titled 'Getting Started' will appear. Click on "Create a New Project" and enter a file name for the project. A "New Project' Dialog window will appear. In this AppNote we will be designing memory for the Spartan II Architecture, so under Target Architecture choose "Spartan II" and under the Design Entry heading check off the "VHDL" radio button. In the Directory Field, enter a directory name where you would like the project to be stored. Click OK.
A window with several directories of predesigned elements will appear. We will be implementing a block ROM. Click on
Basic Elements -> Memory Elements.The memory elements available will be shown on the right hand side window. Double Click on "Distributed Memory." A new window will open with several options. You can choose between implementing ROM, single-port RAM, dual-port RAM, and SRL-16 based RAM. All distributed memory elements are implemented using the same on-chip ram elements; depending on thedesired memory type some input and output signals will not be used. The depth and width of the memory element can also be selected.
Give the memory component a name, "myrom" by typing it into the component name field.The automatically generated vhdl file will be named "myrom.vhdl."
Click the "ROM" radio button and select a data depth of 256 and a data width of 16 bits.This will implement a 4096 Kb block of memory.
Click next.In the following stage, you may choose to have registered or non-registered inputs and outputs. The number of pipeline stages can also be selected. Increasing the number of pipeline stages(latency) will increase throughput. The initial contents of the RAM can also be specified by providing a ".coe" file. An example .coe file for the 16 x 256 bit ROM is shown below:
memory_initialization_radix=2;The ellipsis (...) replaces 251 more lines of binary data. Data can also be entered in hex or decimal, by changing the memory_initialization_radix to the appropriate number. Subsequent memory locations are separated by new line characters, and a semicolon signifies the end of data. Comments can also be added to .coe files after a semi colon but this sometimes results in errors.
memory_initialization_vector =0000000000000000
0000000000001100
0000000000011001
0000000000100101
....
0000011111111110;
To load the .coe file, click on the "Load Coefficients" button and select the desired file.To ensure that the correct data is being used click on the "Show Coefficients" button.
Click on "Generate"
If no error messages appear,
You have successfully added the component to your project. Several files
will be created, but the essential ones are the .vhd and .xco files.
All others can be regenerated easily. The generated module can then
be incorporated into your design just like any other vhdl module. Simply
connect the required signals to the component when it is instantiated in
any higher level vhdl module. For the ROM module, all that is required
are input address lines, and output data lines. Open the myrom.vhd
file to view the input and output specifications.
*Note: Modules using Core Generator do not use generic input and output
width parameters. Every time the desired parameters are changed, the
parameters must be altered in Core Generator and the module regenerated.
However, the following error message may appear:
"Not all output products were generated successfully. Please check
the console or coregen.log for details."
The logfile window near the bottom of the Xilinx Core Generator Window will
read "ERROR: Elaboration of Core Distributed Memory Failed."
In this case, a .vhd file will still be generated, but CoreGen will
not generate the .xco file necessary for incorporation into your project.
This is due to a bug in Xilinx Core Generator 4. If this is the case
CoreGen generated modules can still be included in your code. However,
you must run Coregen directly from Xilinx Project Navigator.
Implementing CoreGen Generated Modules from within Project Navigator
To implement CoreGen Generated modules using Project Navigator, the higher
level VHDL modules that include entity descriptions for the desired coregen
modules should be written first, and added to a project created in Xilinx
Project Navigator. The entity descriptions required can be taken
from the vhd files generated above. For information on using Project
navigator, see <link to Alesya's page here>. Once the higher
level vhd files (that will use the CoreGen modules that you will create)
are added to a Project Navigator project, there will be a question mark icon
beside every entity that does not yet exist. Right click on the question
mark icon that corresponds to the coregen module you would like to add, and
choose new source. A menu of source types will appear**.
Choose CoreGenIP and enter a file name for the new module.The Xilinx Core Generator will automatically open. From here, simply follow the steps given above to create a new module. Click Generate to generate the .vhd and .xco files, and the module will be automatically added to your project in Project Navigator. In the Sources window, the question mark will be replaced by a .xco icon.Click Next.
The CoreGen Module has been added to your project.
To edit the CoreGen Module, click on the corresponding icon in the
sources window. In the processes window, double-click on "manage cores"
To regenerate the CoreGen Module, click on the corresponding icon in the
sources window. In the processes window, double-click on "regenerate
core"
**Note: To call CoreGenIP from Project Navigator, the Project Design Flow must be set to VHDL or Verilog, not EDIF. To set the Design flow, right click on the Top-level Project Icon in the Sources window, and choose DesignFlow -> VHDL.
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