-------------------------------------------------
-- Serial port testing application
--	displays serial port byte information on two
-- led's 
--
library ieee;
use ieee.std_logic_1164.all;

package serialPort_pkg is

component serialPort
 generic (OutDivisor: positive := 1311;  -- use this to control baud rate
									  -- defaults to 9600
		 InDivisor: positive := 82);   -- use this to clock to receiver
		 							  -- must be set to 16 times smaller than
		 							  -- Divisor1
port (clock:				IN std_logic; -- global clock freq 25.175MHz (pin 91)  
	  soutclr, 							  -- synchronous clear for the RS232 output
	  reset:				IN std_logic; -- resets clock divider

      serialin:  			IN STD_LOGIC; -- serial data stream in from PC
	  serialout: 			out std_logic; -- serial data stream sent to PC       
      
	  SerialInData: 			out STD_LOGIC_VECTOR(7 downto 0); -- 8 bit data word to be read
      input_data_valid: 		out STD_LOGIC;  -- indicates data word on q is valid
      
	  serialOutData:  in std_logic_Vector(7 downto 0); -- 8 bit data word to be loaded to be serially sent
      out_load: 		IN STD_LOGIC;  -- should transition high to parallel load data word to be 
      							   -- sent out the serial port to the PC
      enableSerialOut: 	in STD_LOGIC;  -- enable to serialPort out
      
      outReady:   	out STD_LOGIC  -- signal to indicate the register has transmitted the data word
    								   -- and is ready to receive/load a new data word 
     );

end component serialPort;
end package serialPort_pkg;

library ieee;
use ieee.std_logic_1164.all;
library work;
use work.RS_232_In_pkg.all;
use work.RS_232_Out_pkg.all;

entity serialPort is 
generic (OutDivisor: positive := 1311;  -- use this to control baud rate
									  -- defaults to 9600
		 InDivisor: positive := 82);   -- use this to clock to receiver
		 							  -- must be set to 16 times smaller than
		 							  -- Divisor1
port (clock:				IN std_logic; -- global clock freq 25.175MHz (pin 91)  
	  soutclr, 							  -- synchronous clear for the RS232 output
	  reset:				IN std_logic; -- resets clock divider

      serialin:  			IN STD_LOGIC; -- serial data stream in from PC
	  serialout: 			out std_logic; -- serial data stream sent to PC       
      
	  SerialInData: 			out STD_LOGIC_VECTOR(7 downto 0); -- 8 bit data word to be read
      input_data_valid: 		out STD_LOGIC;  -- indicates data word on q is valid
      
	  serialOutData:  in std_logic_Vector(7 downto 0); -- 8 bit data word to be loaded to be serially sent
      out_load: 		IN STD_LOGIC;  -- should transition high to parallel load data word to be 
      							   -- sent out the serial port to the PC
      enableSerialOut: 	in STD_LOGIC;  -- enable to serialPort out
      
      outReady:   	out STD_LOGIC  -- signal to indicate the register has transmitted the data word
    								   -- and is ready to receive/load a new data word 
     );
end serialPort;


architecture behaviour of serialPort is

component clkdiv is
   -- default to .75H
   -- 25.175 MHz/ (2**24) /2
   generic (Divisor: positive :=33554432); -- clock division rate
   port(fast_clock : in STD_LOGIC;
        reset      : in STD_LOGIC;
        slow_clock : buffer STD_LOGIC);
end component clkdiv;

signal serial_output_clock : std_logic;
signal serial_input_clock : std_logic; 

begin
	serialinclkdiv : clkdiv
	 	generic map( Divisor => InDivisor) 
  		port map(
				fast_clock => clock, 
				reset => reset, 
				slow_clock => serial_input_clock
			);

	serialoutclkdiv : clkdiv
	 	generic map( Divisor => OutDivisor) 
  		port map(
				fast_clock => clock, 
				reset => reset, 
				slow_clock => serial_output_clock
			);

	serialinput : RS_232_In 
		port map(
					clock => serial_input_clock,
					shiftin => serialin,
					q => SerialInData,
					data_valid => input_data_valid
     			);

	serialoutput: RS_232_Out
		port map(
					clock => serial_output_clock,
					enable => enableSerialOut,
					sset => soutclr,
					load =>	out_load,
					data => serialOutData,		
		            shiftout => serialout,
					ready => outReady
				); 	
end behaviour;