--clockdiv.vhd
----------------------------------------------------
--divides down the system clock for slower clockrates
----------------------------------------------------
-- borrowed from traffic light example in EE552 class 
-- notes

LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 

ENTITY clkdiv IS
   -- default to .75H
   -- 25.175 MHz/ (2**24) /2
   generic (Divisor: positive :=33554432); -- clock division rate
   port(fast_clock : in STD_LOGIC;
        reset      : in STD_LOGIC;
        slow_clock : buffer STD_LOGIC);
END clkdiv;

architecture behaviour of clkdiv is

begin
	clock_divider: process (fast_clock) is
   		variable c:natural range 0 to Divisor;     
   	begin
      	if rising_edge(fast_clock) then 
      		if reset ='1' then
 				c:= 0;
				slow_clock <= '0';
           	else
         		c := (c + 1);
         		if c=Divisor then
            		slow_clock <= not slow_clock;
            		c := 0;
	   			end if;
         
      		end if;
      	end if;
   end process clock_divider;
end behaviour;