Signal Latching 

Brought to you By DPF, 

Ben Talbot, David Ng, Mel Lumague, Nitin Parimi, Emy Egbogah

A couple of groups over the course of the semester asked me how to latch a signal, so when a signal coming from a slower clock domain will only produce a high/low pulse for a single clock cycle in the faster domain. After providing the code directly to groups I thought I would post it for students next year.

This is an example of how the system works, with the code. 

send_output:process( syn_clock )
    variable output_state : integer range 0 to 1 := 0;
    begin
        if rising_edge( syn_clock ) then
            if reset = '1' then
                output_state := 0;
                syn_button_out <= '0';
            elsif pb_debounced = '1' and output_state = 0 then
                output_state := 1;
                syn_button_out <= '1';
            elsif pb_debounced = '0' and output_state = 1 then
                output_state := 0;
                syn_button_out <= '0';
            else
                syn_button_out <= '0';
            end if;
        end if;
    end process;

In this system:

pb_debounced - the input signal that is a goes high for numerous clock cycles

output_state - the output state of the signal latcher

syn_button_out - single high/low clock output signal

syn_clock - fast clock to sink the single enable pulse to

The code is fairly self explanatory. When the system gets the long enable pulse it set outputs a high on the synchronized signals and changed states, waiting for the enable pulse to go low again.