Infrared (IR) Receiver

Group Members:  Nitin Parimi, Ben Talbot, Emy Egbogah, Mel Lumague, Dave Ng
This student application note is aimed at providing an understanding of common coding schemes associated with infrared transmitters and the scheme that we used to decode an IR signal.Our project (a digital picture frame) requires a remote controller to scroll back and forth through pictures, which are all stored in RAM memory, until the desired one is displayed to a monitor.Therefore, the prerequisites involved in using a remote controller are threefold.First, the coding scheme of the controller must be determined.Second, the signal from the remote must be decoded in order to determine which button on the remote was pressed.Thirdly, once the IR receiver determines which button was pressed, the FPGA must send out the appropriate signal so that the user request is correctly processed.The emphasis of this particular application note focuses on the second stage of this process, which is the decoding of a pulse-width modulated signal.

 

Background Information on Common Coding Schemes

There are several methods of encoding IR bits, but two of the most common schemes are the RECS-80 and the RC-5 techniques.In the REC-80 technique, the bits are pulse-length modulated according to the logic value associated with a bit.A logic '0' (or low) bit is represented by a pulse of duration 'T', followed by a time of 2T without a pulse.A logic '1' (or high) bit is represented by a pulse of duration 'T', followed by a time of 3T without a pulse.The duration time 'T' of a pulse varies depending on the manufacturer of the IR transmitter (remote control) and can be determined using an oscilloscope and timing analysis methods.The RC-5 technique is characterized by the fact that both logic high and low values have the same time duration.A logic high value is represented by a low to a high (rising edge) transition and a logic low value is represented by a high (falling edge) to a low transition.

Encoding Scheme used by the Universal Remote Controller

However, neither of these encoding schemes was used in the TV remote controller that was used in our project.We used the IS1U60 IR receiver chip to detect an incoming signal that was transmitted by the X-10 Universal Remote Control.To determine the encoding scheme of the transmitter, simply hook up the receiver chip to an oscilloscope.A square wave pattern will result indicating how each of the logic levels (high and low) is represented.The next task is to determine how the logic levels are being represented.In this particular encoding scheme, pulse-width modulation is utilized.High and low bits are both represented by pulses, but they are differentiated by the fact that pulses representing a logic high bit have a longer duration than those representing logic low bits.This coding scheme is known as the NEC-136 scheme.  Further, this encoding scheme involves a start bit whose associated pulse duration is longer than both the other pulses.Each data packet transmitted by the remote starts with a start bit that is followed by a pulse pattern representing '1's and '0's.Each button on the remote sends out a different data packet (that is indicated on an oscilloscope by a different pulse pattern).

An example of the square-wave pulse pattern resulting from the 'Play' button on the remote is shown below:

Decoding the Received IR Pulse-Modulated Signal

The next task in using a remote controller is to decode the received pulse-modulated signal into the appropriate bits using the FPGA.The bit pattern of the 'Play' command is '1100001000110000'.In order to recognize this pattern, a strategy for distinguishing '1's from '0's must be implemented.A top level diagram illustrating the strategy is shown and explained below:

The system above uses a counter to time how long an input pulse remains in its 'high' state.The counter starts timing when a rising edge is detected from the data packet.The counter continues to count the number of clock cycles the signal is high until a falling edge is detected.When a falling edge is detected, the value for 'high time' of the pulse is stored in a clocked register, which is disabled until a falling edge is detected.At this point, the counter is reset and ready to measure the duration of the next incoming pulse.The D flip-flop is used so that the present value of the counter is sent to the register before the next rising edge enables the counter.

The data (i.e. the number of clock cycles) is sent to three comparators to determine what type of bit has been received.Each of the comparator units compares the incoming data to a range of predefined duration lengths that have been set to define the durations of the various bits.When the nature of the bit has been determined (i.e. 1, 0, or start bit), the bit enters a finite state machine (The entry point to the finite state machine is indicated on figure 2 as 'fsm').The finite state machine detects the pattern of the bits in the data packet and as a result, detects what type of command has been sent from the remote control. A copy of each of the VHDL files used in the design of the IR receiver is attached to this student application note.  A brief description of the key files is presented in the following:

irdecoder.vhd - This file is designed based on the design illustrated in Figure 2 (the Top Level Diagram of Pulse-Width Modulated Signal Decoder).  This file determines the nature of an incoming pulse (i.e. what type of bit, '0', '1', or start, that the pulse is associated with).  It sends the associated bit to the finite state machine (fsm.vhd).

irgreater.vhd - This file is a modified version of the max2plus wizard generated file that compares whether one number is greater than another.  This program is modified to include a generic width of the incoming data as opposed to a set value coming into the comparator.  This modified version of a comparator increases the component's flexibility and eliminates the need for several "greater than" comparators to be used. This comparator is used in the process to determine the type of bit that is associated with a pulse by comparing pulse durations.

irlesser.vhd - This file is a modified version of the max2plus wizard generated file that compares whether one number is less than another.  This program is modified to include a generic width of the incoming data as opposed to a set value coming into the comparator.  This modified version of a comparator increases the component's flexibility and eliminates the need for several "less than" comparators to be used.  This comparator, along with the irgreater.vhd comparator, is used in the process to determine the type of bit that is associated with a pulse by comparing pulse durations.

registerN.vhd -  This file is the implementation for the register shown in figure 2 above.  Its primary function is to synchronize timing between the pulses coming into the counter and the pulse duration values entering the comparators.

fsm.vhd -  This file is the finite state machine to detect the pattern of one of the six remote control button inputs.  This pattern detector will vary according to the remote control used and their varying bit patterns.