-------------------------------------------------------------------------------
-- File: fsm.vhd
--
-- Project: DPF
-- Created by: Nitin Parimi, Ben Talbot 
-- Date: 3/4/02
--
-- Purpose: Detects PLAY,REW,FF,STOP,PAUSE,REC sequences on an incoming Value
--			Stream
--			-Modified from the EE552 Lab1
--
-- Inputs:  	clock       <- Clock to preform state changes on
--              reset       <- reset state machine to initial set
--				valueStream <- incoming value stream
--								('1'<="11",'0'<="00",OFF<="10, START<="01")
--	        	stream_valid <- Value on the incoming stream is valid
--				inputsequence <- ending characters after the initial 8
--
-- Outputs:     mathc 	->  command was found
--
-- External Connections:
--      
-------------------------------------------------------------------------------
library ieee; 
use ieee.std_logic_1164.all; 

entity fsm is
	generic ( cmdWidth : positive := 16); 
    port ( 
	        clock : in std_logic;
			valueStream: in std_logic_vector(1 downto 0); 
        	match: out std_logic;
			reset: in std_logic;
			inputsequence : in std_logic_vector(cmdWidth-1 downto 0);
			stream_valid: in std_logic
		); 
end fsm; 

architecture mixed of fsm is 

-- name states after bit pattern already seen 
type state_type is (sawnull,
					sawstart,
					sawoff,
					saw1, 
					saw11, 
					saw110, 
					saw1100, 
					saw11000, 
					saw110000, 
					saw1100001, 
					saw11000010,
					sawIC1, 
					sawIC2, 
					sawIC3, 
					sawIC4, 
					sawIC5,
					sawIC6, 
					sawIC7, 
					sawIC8, 
					hold_output); 
signal state, next_state :state_type; 
signal reset_match : std_logic;

begin 

combinational_logic :process(valueStream, state) 
begin 

-- The default value is no match
match <= '0'; 
case state is 
		when sawnull => 
				reset_match <= '0';
                if valueStream = "01" then 
                        next_state <= sawstart; 
                else 
                        next_state <= sawnull; 
                end if; 
   		when sawstart => 
                if valueStream = "10" then 
                        next_state <= sawoff; 
                else 
                        next_state <= sawnull;
                end if; 
        when sawoff => 
                if valueStream = "11" then 
                        next_state <= saw1; 
                else 
                        next_state <= sawnull;
						--play <= '1'; 
                end if; 
        when saw1 => 
                if valueStream = "11" then 
                        next_state <= saw11; 
                else 
                        next_state <= sawnull;
						--play <= '1'; 
                end if; 
        when saw11 => 
                if valueStream = "00" then 
                        next_state <= saw110; 
                else 
                        next_state <= sawnull; 
                end if; 
        when saw110 => 
                if valueStream = "00" then
                        next_state <= saw1100; 
                else
                        next_state <= sawnull; 
                end if; 
		when saw1100 => 
                if valueStream = "00" then
                        next_state <= saw11000; 
                else
                        next_state <= sawnull; 
                end if; 
		when saw11000 => 
                if valueStream = "00" then
                        next_state <= saw110000; 
                else
                        next_state <= sawnull; 
								end if;
		when saw110000 => 
                if valueStream = "11" then
                        next_state <= saw1100001; 
                else
                        next_state <= sawnull; 
                end if; 
		when saw1100001 => 
                if valueStream = "00" then
                        next_state <= saw11000010; 
                else
                        next_state <= sawnull; 
                end if; 
		when saw11000010 => 
                if valueStream = inputsequence(15 downto 14) then
                        next_state <= sawIC1; 
                else
                        next_state <= sawnull; 
                end if; 
		when sawIC1=> 
                if valueStream = inputsequence(13 downto 12) then
                        next_state <= sawIC2; 
                else
                        next_state <= sawnull; 
                end if; 
		when sawIC2=> 
                if valueStream = inputsequence(11 downto 10) then
                        next_state <= sawIC3; 
                else
                        next_state <= sawnull; 
                end if; 
		when sawIC3=> 
                if valueStream = inputsequence(9 downto 8) then
                        next_state <= sawIC4; 
                else
                        next_state <= sawnull; 
                end if; 
		when sawIC4=> 
                if valueStream = inputsequence(7 downto 6) then
                        next_state <= sawIC5; 
                else
                        next_state <= sawnull; 
                end if; 
		when sawIC5=> 
                if valueStream = inputsequence(5 downto 4) then
                        next_state <= sawIC6; 
                else
                        next_state <= sawnull; 
                end if; 
		when sawIC6=> 
                if valueStream = inputsequence(3 downto 2) then
                        next_state <= sawIC7; 
                else
                        next_state <= sawnull; 
                end if; 
		when sawIC7=> 
                if valueStream = inputsequence(1 downto 0) then
                        next_state <= sawIC8; 
                else
                        next_state <= sawnull; 
                end if; 
		when sawIC8=>
					match <= '1';
                	next_state <= hold_output;
					reset_match <= '1';
		when hold_output =>
					match <= '0';
					next_state <= sawnull;  
									
end case; 

end process combinational_logic; 
  

state_register : process(reset, clock) 
begin 
    if reset = '1' then 
            -- reset state 
            state <= sawnull; 
    elsif rising_edge(clock) then 
            -- advance to next state
			if stream_valid = '1' or reset_match = '1' then
            	state <= next_state;
			end if;
    end if;  
end process state_register; 


end mixed;