You will find that as you write your reports, they are going to start getting longer, and likely will become harder to manage. This application note outlines a possible way you can organize:
A. Your INDEX to VHDL Code and associated Code
B. Your SIMULATION INDEX to Test Cases / Verification
INDEX to VHDL Code:
VHDL Code will likely be placed in one of your appendicies. For the final three reports, the VHDL design is required, providing all code as indexed. An excellent way to organize this appendix is to divide your project into several main components. For each of these components include any related packages, followed by the code. The VHDL index to the packages and code can be easily integrated into this appendix. The VHDL index requires all packages, and for you to provide the entity name, a one sentence description, and a label of "not compiled", "compiled-no errors", or "simulated-no known bugs".
An excellent format for this follows:
-----------------------------------------------(page 1)------------------------------------------------
APPENDIX A: VHDL CODE (title page)
-----------------------------------------------(page 2)------------------------------------------------
INDEX to VHDL packages and code
A.1 Component 1
A.1.1 Component 1 Package 1 "file_name.vhd"
A.1.2 Component 1 VHDL Code "file_name.vhd"
A.1.2.a Entity 1
- a one sentence description of the entity
- "compiled-no errors", "compiled-no errors", or "not compiled"
A.2 Component 1
A.2.1 Component 1 Package 1 "file_name.vhd"
A.2.2 Component 1 VHDL Code "file_name.vhd"
A.2.2.a Entity 1
- a one sentence description of the entity
- "compiled-no errors", "compiled-no errors", or "not compiled"
-------------------------------------(page after the index)----------------------------------------
Actual VHDL code following class coding standards.
--------------------------------------------------------------------------------------
SIMULATION INDEX:
The simulation index will also likely be placed in one of your appendicies. For the final three reports, verification is required. An excellent way to organize this appendix is to divide your project into several main modules that can be tested separately. Finally, all modules can be tested together. For each of these modules include all testing waveforms. Each testing waveform should be annotated, and will likely test several tests. As you are required to proceed each simulation run by a description page of what is being tested and what is shown, this page can be used to separate one waveform from the next. At the bottom of each descriptive page, you can answer the following questions: What is the maximum speed? What is the critical path? What would you change to make it faster?
An excellent format for this follows (note, this format can also be used for the testbench index).
-----------------------------------------------(page 1)------------------------------------------------
APPENDIX B: SIMULATIONS AND VERIFICATION (title page)
-----------------------------------------------(page 2)------------------------------------------------
INDEX to SIMULATIONS AND VERIFICATION
B.1 MODULE 1
B.1.1 Title Page of the first simulation for Module 1
- this is followed by the annotated format.
B.1.2 Title Page of the second simulation for Module 1
- this is followed by the annotated format.
B.2 MODULE 2
B.2.1 Title Page of the first simulation for Module 2
- this is followed by the annotated format.
B.2.2 Title Page of the second simulation for Module 2
- this is followed by the annotated format.
.
.
.
B.N ENTIRE PROJECT
B.N.1 Title Page of the first simulation for the entire system
- this is followed by the annotated format.
B.N.2 Title Page of the second simulation for the entire system.
- this is followed by the annotated format.
-------------------------------------(page after the index)----------------------------------------
Actual Title Pages and Simulations
----------------------------------------------------------------------------------------------------------
Using these formats can help you keep your project report manageable, and are easily expandable as you add new simulations and code to your project. Any questions can be directed to our group members.
Group Members:
Darren Gonek
Guillermo Barreiro
Andrew Ling
Shyam Chadha
Timmy Li
Reid Orsten
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