This application note describes the EE-100 Module and the CS8900A Ethernet Controller in 8-bit I/O mode. The EE-100 Module uses the CS8900A has it’s Ethernet controller and was bought from www.embeddedether.net. The CS8900A is a low cost yet powerful Ethernet Controller developed by Crystal/Cirrus Logic. More information can be found at www.cystal.com.
Terminology
Packet - the physical structure that is transmitted over the Ethernet network. The packet includes the preamble, Start-of-Frame Delimiter (SFD), Destination Address (DA), Source Address (SA), Length, Data, pad bits (if necessary), and Frame Check Sequence (FCS/CRC).
Frame - portion of the packet from the Destination Address to the Frame Check Sequence.
The Embedded Ethernet Board, EE-100 Module, can be purchased at
or an alternative Embedded Ethernet Board can be found at
· The default setting of the CS8900A is I/O mode.
· Interrupts in 8-bit mode are not supported
· Auto increment feature of the PacketPage Pointer is not supported in 8-bit mode
· Address and Data is 16-bits
· Most of the information in this app note is from the following resources:
To ensure that the CS8900A is connected, an initial test can be performed. The value of PacketPage Pointer is 0x3XXX. Test that the most significant byte is = 3:
1) Address = PacketPage Pointer = 0x000a
2) Enable aen pin and ior pin
3) ValueL = DataPin[8]
4) Disable aen pin and ior pin
5) Address = PacketPage Pointer + 1 = 0x000b
6) Enable aen pin and ior pin
7) ValueH = DataPin[8]
8) Disable aen pin and ior pin
9) Check ValueH[7 to 4] = 3, to indicate a good connection
8-bit Mode
I/O mode is the default configuration and is enable after reset. To access the CS8900A in 8-bit mode, 8 I/O ports are used. Each I/O port is 16 bits. The following table gives a brief summary of each port:
Figure 2: Mapping of the I/O Mode Registers [2]
|
Offset |
Type |
Description |
|
0x0000 |
Read/Write |
Receive/Transmit Data (Port 0) |
|
0x0002 |
Read/Write |
Receive/Transmit Data (Port 1) |
|
0x0004 |
Write |
TxCMD (Transmit Command) |
|
0x0006 |
Write |
TxLenght (Transmit Length) |
|
0x0008 |
Read |
Interrupt Status Queue |
|
0x000a |
Read/Write |
PacketPage Pointer |
|
0x000c |
Read/Write |
PacketPage Data (Port 0) |
|
0x000e |
Read/Write |
PacketPage Data (Port 1) |
To get the physical address of the port, take the base I/O address, default locations is 0x0300, and add the corresponding offset.
The EE-100 Module uses 15 pins to communicate with the CS8900A: 8-bit data pin, 4-bit address pin, 1-bit write bit, 1-bit read bit, and 1-bit address enable bit.
Before any operation can be performed, the CS8900A must be configured at power up or after a reset. Page 18 of the CS8900A product datasheet describes the different kinds of reset. When each reset, the chip checks the internal pin EEDI to see if an EEPROM is present. An external EEPROM can be used to initialize the CS8900A. We did not use an EEPROM, thus I will not go into detail the process of using an EEPROM; section 3.4 describes this process in detail. If EEDI is low, indicating no external EEPROM is present, the default configuration is loaded into the registers; page 19 illustrates the default register values.
To access the CS8900A’s internal registers, the PacketPage configuration is used. The address of the register is written to the PacketPage Pointer Port and the corresponding data of the register is mapped into PacketPage Data Port. The procedure to write to individual registers using the EE-100 Module is describe below:
1) DataPin[8] = least significant 8-bit of the address of the register
2) Address = PacketPage Pointer = 0x000a
3) Enable aen pin and iow pin, then disable iow pin
4) DataPin[8] = most significant 8-bit of the address of the register
5) Address = PacketPage Pointer + 1 = 0x000b
6) Enable aen pin and iow pin, then disable iow pin
7) DataPin[8] = least significant 8-bit of the value to be written to the register
8) Address = PacketPage Data = 0x000c
9) Enable aen pin and iow pin, then disable iow pin
10) DataPin[8] = most significant 8-bit of the value to be written to the register
11) Address = PacketPage Data + 1 = 0x000d
12) Enable aen pin and iow pin, then disable iow pin
This procedure is used to initialize the CS8900A registers. Chapter 4 describes the PacketPage architecture and gives detailed information of each register. I will describe some important registers and individual bits:
1) Register 15: Self Control
- bit 6 (reset) => reset the chip when bit is set
2) Register 16: Self Statue
- bit 7 ( INITD) => indicates that default configuration is done when set
3) Register 5: Receiver Control
- bit 8 (RxOKA) => when set, the CS8900A will receive frames that have a valid CRC and valid length , 64 <= length <= 1518 bytes.
- bit A (IndividualA) => receive frames from the same destination address that is loaded into Individual Address Register
- bit B (BroadcastA) => receive frames from the destination address = 0xFFFF FFFF FFFF
- bit D (RuntA) => accepts frames that are less than 64 bytes
4) Register 13: Line Control
- pin 6 (SerRxON) => when set, receiver is enable
- pin 7 ( SerTxOn) => when set, transmitter is enable
5) Individual Address (IEEE address)
- The 48-bit IEEE address is stored in. the first bit must be 0
Only the frame portion of the Ethernet packet is transferred to the host from the CS8900A. The preamble and SFD is stripped by the CS8900A.
In the Application Note CS8900A in 8-bit Mode, It states that interrupts in 8-bit mode are not supported. Thus polling is used as an alternative. Polling is checking at regular intervals. In our case to receive an Ethernet frame, poll the Rx Event Register. When the register indicates that there is an incoming frame the following process is done (assuming that the I/O base is located at 0x300) [3]:
1) Read the RxStatus word (same data as RxEvent, register) from data port 0. Read this high order byte 0x301 first, then low order byte 0x300.
Note: it is very important to read the RxStatus and RxLength high order bytes first.
2) Read the RxLength word (the frame length) from data port 0. Read this high order byte 0x301 first, then low order byte 0x300.
3) Begin reading the frame data, 0x300 then 0x301, 0x300 then 0x301 until the entire frame has been transferred to host memory.
The following process is an example of how the above process can be executed when using the EE-100 Module:
// Poll the Receive Register to see if frame is present
1) DataPin[8] = 0x24
2) Address = PacketPage Pointer = 0x000a
3) Enable aen pin and iow pin, then disable iow pin
4) DataPin[8] = 0x01
5) Address = PacketPage Pointer + 1 = 0x000b
6) Enable aen pin and iow pin, then disable iow pin
7) Address = Port Data = 0x0c
8) Enable aen pin and iorpin
9) ValueL = DataPin[8]
10) Disable aen pin and iorpin
11) Address = Port Data +1 = 0x0d
12) Enable aen pin and iorpin
13) ValueH = DataPin[8]
14) Disable aen pin and iorpin
15) Check least significant bit of value, packet present if set else poll register again
// frame is present, receive frame 1 byte at a time, notice I receive the high order byte first. The first value receive is the Length byte
16) Address = Port RxTxData +1 = 0x01
17) Enable aen pin and iorpin
18) ValueH = DataPin[8]
19) Disable aen pin and iorpin
20) Address = Port RxTxData = 0x00
21) Enable aen pin and iorpin
22) ValueL = DataPin[8]
23) Disable aen pin and iorpin
// Continue this process until the entire frame is received.
Transmission of a frame occurs in two steps[4]:
1) Bid for buffer space on the chip by writing the transmit command to the TxCMD port and the length to TxLength port then checking the BusSt register.
2) If space is available begin writing the data, a byte at a time, to Receive/Transmit data port 0.
The following process is an example of how the above process can be executed when using the EE-100 Module:
// Send the transmit command to TxCMD port
1) DataPin[8] = 0xc0 // transmit command = 0x00c0
2) Address = Port TxCMD = 0x0004
3) Enable aen pin and iow pin, then disable iow pin
4) DataPin[8] = 0x00 // transmit command
5) Address = Port TxCMD +1 = 0x0005
6) Enable aen pin and iow pin, then disable iow pin
// Send the Length of the Frame to TxLength port
7) DataPin[8] = Least Significant 8 bit of Length
8) Address = Port TxLength = 0x0006
9) Enable aen pin and iow pin, then disable iow pin
10) DataPin[8] = Least Significant 8 bit of Length
11) Address = Port TxLength +1 = 0x0007
12) Enable aen pin and iow pin, then disable iow pin
//Check the Bus Status
13) DataPin[8] = 0x38
14) Address = PacketPage Pointer = 0x000a
15) Enable aen pin and iow pin, then disable iow pin
16) DataPin[8] = 0x01
17) Address = PacketPage Pointer + 1 = 0x000b
18) Enable aen pin and iow pin, then disable iow pin
19) Address = PortData = 0x0c
20) Enable aen pin and iorpin
21) ValueL = DataPin[8]
22) Disable aen pin and iorpin
23) Address = PortData +1 = 0x0d
24) Enable aen pin and iorpin
25) ValueH = DataPin[8]
26) Disable aen pin and iorpin
27) Check if least significant bit = 0, if set then ready to transmit else wait until set
// Transmit word
28) DataPin[8] = least significant 8-bit of the value written to the register
29) Address = Port RxTxData = 0x00
30) Enable aen pin and iow pin, then disable iow pin
31) DataPin[8] = most significant 8-bit of the value written to the register
32) Address = Port RxTxData + 1 = 0x01
33) Enable aen pin and iow pin, then disable iow pin
// Repeat this process this the entire frame is set
[1] – TechFest Ethernet Technical Summary, http://www.techfest.com/networking/lan/ethernet2.htm
[2] – p 75, Table 17: I/O Mode Mapping, Cirrus Logic
Product Datasheet,
http://www.cirrus.com/pubs/cs8900a-4.pdf?DocumentID=532
[3] – p 2, Frame Reception, USING THE CRYSTAL CS8900A
IN 8-BIT MODE, http://www.cirrus.com/pubs/an181.pdf?DocumentID=259
Sample code in BASIC:
Matthew Daughtrey, www.embededether.net
Gary T. Desrosiers, www.embeddedethernet.com
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