-- sliptester.vhd hh
-- used to display received packets on the LED
-- left button to reset
-- right button to look at next packet.
-----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all;
library work;
use work.sliptester_pkg.all;
entity sliptester is

	port(	-- button controls
			nextpacket: in std_logic;
			treset:	in std_logic;
			-- left side
			tsysclock:	in std_logic;
			tserialin:	in std_logic;
			--tserialout:	out std_logic;
			tenableserialout:	in std_logic;
			--toutready:	out std_logic;
			-- right side
			tpktRead:	out std_logic;
			tdata_valid:	out std_logic;
			tdata_out_left:	out std_logic_vector(6 downto 0);
			tdata_out_right: out std_logic_vector(6 downto 0);
			reset_but: out std_logic;
			nextpack_but: out std_logic;
			lightaddress: out std_logic
		);
end sliptester;

architecture mixed of sliptester is
component slipcontrol is
	port(	-- left side
			sysclock:	in std_logic;
			reset:	in std_logic;
			serialin:	in std_logic;
			serialout:	out std_logic;
			enableserialout:	in std_logic;
			outready:	out std_logic;
			-- right side
			pktRead:	out std_logic;
			divClock:	in std_logic;
			data_valid:	out std_logic;
			data_out:	out std_logic_vector(bytesize - 1 downto 0);
			address_in: in std_logic_vector(ram_address_width - 1 downto 0);
			out_load:	in std_logic;
			serial_out_data:	in std_logic_vector(bytesize-1 downto 0);
			out_finished: in std_logic;
			internal_data: out std_logic_vector(bytesize-1 downto 0)
		);
end component slipcontrol;

component leddecoder is
	generic ( ledwidth : positive := 7 );
	port(value : in std_logic_vector(3 downto 0);
  	   	 led : out std_logic_vector(ledwidth-1 downto 0)
		);
end component leddecoder;

component clkdiv IS
   -- default to .75H
   -- 25.175 MHz/ (2**24) /2
   generic (Divisor: positive :=33554432); -- clock division rate
   port(fast_clock : in STD_LOGIC;
        reset      : in STD_LOGIC;
        slow_clock : buffer STD_LOGIC);
END component clkdiv;
---
signal addr_up, slowclock,dispclk: std_logic;
signal localaddress_in: std_logic_vector(ram_address_width-1 downto 0);
signal data_outtoLED, tempdata: std_logic_vector(bytesize - 1 downto 0);
signal rightdataout, leftdataout: std_logic_vector(3 downto 0);
signal one, zero: std_logic;
signal zerovector: std_logic_vector(bytesize - 1 downto 0);
signal dummyenableserialout, resetinv: std_logic;
signal d_internaldata: std_logic_vector(bytesize - 1 downto 0);
---
begin
one <= '1';
zero <= '0';
zerovector <= "00000000";

slowerclock: clkdiv
	generic map (divisor => rxCLKDivisor)
	port map (fast_clock => tsysclock,
			reset => zero,
			slow_clock => slowclock
	);
dispchangeclock: clkdiv
	generic map (divisor => 12587500)
	port map (fast_clock => tsysclock,
			reset => zero,
			slow_clock => dispclk
	);
slipRX: slipcontrol
	port map(	-- left side
			sysclock => tsysclock,
			reset => resetinv,
			serialin => tserialin,
			--serialout => zero,
			enableserialout => dummyenableserialout,
			--outready,
			-- right side
			pktRead => tpktRead,
			divClock => slowclock,
			data_valid => tdata_valid,
			data_out => tempdata,
			address_in => localaddress_in,
			out_load => zero,
			serial_out_data => zerovector,
			out_finished => zero,
			internal_data => d_internaldata
		);
LEDDisp1: leddecoder
	generic map ( ledwidth => 7 )
	port map (value => leftdataout,
  	   	 led => tdata_out_right
		);
LEDDisp2: leddecoder
	generic map (ledwidth => 7)
	port map(value => rightdataout,
		led => tdata_out_left
	);

LEDstuff: for i in 0 to 3 generate
          rightdataout(i) <= data_outtoLED(i);
		  leftdataout(i) <= data_outtoLED(4+i);
	end generate;
--LEDstuff: for i in 0 to 3 generate
	--	rightdataout(i) <= d_internaldata(i);
	--	leftdataout(i) <= d_internaldata(4+i);
	--end generate;

display: process(dispclk)
variable dswitching: std_logic;
begin
if rising_edge(dispclk) then
	if dswitching = '0' then
		data_outtoLED <= tempdata;
		lightaddress <= '1';
	else
		data_outtoLED <= localaddress_in(7 downto 0);
		lightaddress <= '0';
	end if;
	dswitching := not dswitching;
resetinv <= not treset;
		if resetinv = '1' then
			reset_but <= '0';
			localaddress_in <= (others => '0');
		else
			reset_but <= '1';
			addr_up <= not nextpacket;
			if addr_up = '1' then
				nextpack_but <= '0';
				localaddress_in <= localaddress_in + '1';
			else nextpack_but <= '1';
			end if;
		end if;


end if;
end process;

end mixed;