-------------------------------------------------
-- slipcontrol.vhd hh
-- used to coordinate the slip and slipbuffer components
-- March 23, 2002
-- Steven Dytiuk
-------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.slip_pkg.all;

entity slipcontrol is
	port(	-- left side
			sysclock:	in std_logic;
			reset:	in std_logic;
			serialin:	in std_logic;
			serialout:	out std_logic;
			enableserialout:	in std_logic;
			outready:	out std_logic;
			-- right side
			pktRead:	out std_logic;
			divClock:	in std_logic;
			data_valid:	out std_logic;
			data_out:	out std_logic_vector(bytesize - 1 downto 0);
			address_in: in std_logic_vector(ram_address_width - 1 downto 0);
			out_load:	in std_logic;
			serial_out_data:	in std_logic_vector(bytesize-1 downto 0);
			out_finished: in std_logic;
			internal_data: out std_logic_vector(bytesize - 1 downto 0)
		);
end slipcontrol;

architecture RTL of slipcontrol is
---
signal write, theclock: std_logic;
signal address: std_logic_vector(ram_address_width - 1 downto 0);
signal data: std_logic_vector(bytesize-1 downto 0);
---
begin
internal_data <= data;

RightPhase: slip
	port map( 
		clock => sysclock,
		soutclr => reset,
		reset => reset,
		serialin => serialin,
		serialout => serialout,
		enableserialout => enableserialout,
		outready => outready,
		serialoutdata => serial_out_data,
		out_load => out_load,
		pktRead => pktRead,
		serialindata => data,
		slip_clock => theclock,
		slip_addr_out => address,
		slip_write_out => write,
		out_finished => out_finished
	);
---
LeftPhase: slipbuffer
	port map(
		slip_byte_in => data,
		slip_clock => theclock,
		slip_address_in => address,
		slip_write_in => write,
		ctrl_clock => divclock,
		ctrl_data_valid => data_valid,
		ctrl_data_out => data_out,
		ctrl_address_in => address_in
	);
end RTL;