-----------------------------------------------
-- SLIPBUFFER.vhd
-- March 21, 2002
-- Steven Dytiuk, NETCON Group
-- For use with SLIP: Stores the received byte
-- into the FPGA RAM for retrieval by the
-- Ethernet state machine
-----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library work;
use work.slip_pkg.all;

entity slipbuffer is
	port (		slip_clock:	in std_logic;
				ctrl_clock: in std_logic;
				ctrl_data_valid: out std_logic;
				slip_byte_in: in std_logic_vector(ram_data_width - 1 downto 0);
				slip_address_in: in std_logic_vector(ram_address_width - 1 downto 0);
				slip_write_in: in std_logic;
				ctrl_data_out: out std_logic_vector(ram_data_width - 1 downto 0);
				ctrl_address_in: in std_logic_vector(ram_address_width - 1 downto 0)
		);
end slipbuffer;

architecture mixed of slipbuffer is
---
signal ctr_line: std_logic_vector(ram_address_width - 1 downto 0);  
		-- contains the address data of either SLIP or Ethernet state machine
signal a2dAddress_in: std_logic_2D(1 downto 0, ram_address_width - 1 downto 0);
signal slip_wi_4MUX: std_logic_vector(0 downto 0);
	-- needed for MUX
signal datavalid_delay1, datavalid_delay2: std_logic;
begin			
buffer_ram: lpm_ram_dq
	generic map(	lpm_width	=> ram_data_width,
					lpm_widthad => ram_address_width,
					lpm_indata 	=> "REGISTERED",
					lpm_outdata	=> "REGISTERED",
					lpm_numwords => ram_data_size,
					lpm_address_control => "REGISTERED")
	port map(		data		=> slip_byte_in,
					we			=> slip_write_in,
					address		=> ctr_line,
					inclock		=> slip_clock,
					outclock	=> ctrl_clock,
					q			=> ctrl_data_out
	);
---
conv_1dto2d: for i in 0 to ram_address_width - 1 generate
                 a2dAddress_in(0,i) <= ctrl_address_in(i);
                 a2dAddress_in(1,i) <= slip_address_in(i);
end generate;
---
Addr_control: lpm_mux
	generic map(	lpm_width	=> ram_address_width,
					lpm_widths	=> 1,
					lpm_size	=> 2 )
	port map(		data		=> a2daddress_in,
					sel			=> slip_wi_4MUX,
					result		=> ctr_line
	);
---					
data_valid: process(ctrl_clock)
	begin
	if rising_edge(ctrl_clock) then
		ctrl_data_valid <= datavalid_delay2;
		datavalid_delay2 <= datavalid_delay1;
		datavalid_delay1 <= not slip_write_in;
		slip_wi_4MUX(0) <= slip_write_in;
			-- needed because input to lpm_mux must be std_logic_vector
	end if;
	end process data_valid;
end mixed;