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-- slip_pkg.vhd STUPIDDDD MP@
-- contains the important constants
-- for use in the SLIP side of our project
-- by Steven Dytiuk
-- March 23, 2002
-------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.RS_232_In_Pkg.all;
use work.RS_232_Out_Pkg.all;

package slip_pkg is
	constant bytesize			:positive	:= 8;
-- constants first used for slip.vhd
	constant inCLKDivisor		:positive	:= 82;
		-- = outCLKDivisor / 16
	constant outCLKDivisor		:positive	:=1311;
		-- = 25,175,000/(2*9600 BAUD)
	constant RXCLKDivisor		:positive	:=13110;
		-- = outclkdivisor * 10
		-- IMPORTANT!! This will be used for the slipbuffer clock from slip.
-- constants first used for slipbuffer.vhd
	constant ram_data_width		:positive	:=bytesize;
	constant ram_address_width	:positive	:=9;
	constant address_zero:std_logic_vector(ram_address_width-1 downto 0):="000000000";
	constant ram_data_size		:positive	:=512;
		-- ram_data_size = 2^(ram_address_width)
-- slip character constants
	constant END_char: std_logic_vector(bytesize - 1 downto 0) := "11000000";
	constant ESC_char: std_logic_vector(bytesize - 1 downto 0) := "11011011";
	constant ESC_END_char: std_logic_vector(bytesize - 1 downto 0) := "11011100";
	constant ESC_ESC_char: std_logic_vector(bytesize - 1 downto 0) := "11011101";
	constant Nothing_Char: std_logic_vector(bytesize - 1 downto 0) := "00000000";
-----
component SLIP is
generic (	TwoWords: positive := 19);
			-- 19 + 1 = 20 words is the size of two incoming RS232 words
			-- used for override on ESCape characters
port (	clock:		in std_logic;	-- pin 91 @ 25.175 MHz
		soutclr:	in std_logic;	-- sync. clear for output
		reset:		in std_logic;	-- reset clock divider
		serialin:	in std_logic;	-- data stream IN
		serialout:	out std_logic;	-- data stream OUT
		serialinData: out std_logic_vector(bytesize - 1 downto 0);
			-- the data packet read in
		input_data_valid: out std_logic; -- indicates data is valid
		serialoutData:	in std_logic_vector(bytesize - 1 downto 0);
			-- the data packet to send out
		out_load:	in std_logic;
			-- pulse high to load the serialOutData and send it
		enableSerialout:	in std_logic;	-- serial out enable
		outReady:	out std_logic;	
			-- indicates we are ready to rx/load a new data word
		pktRead:	out std_logic;  -- pulses high when end is received
		slip_clock: out std_logic;
		slip_addr_out: out std_logic_vector(ram_address_width - 1 downto 0);
		out_finished: in std_logic; -- to send the END control char after packet done
		slip_write_out: out std_logic -- high when sending data to controller
	);
end component SLIP;
-----
component slipbuffer is
	port (		slip_clock:	in std_logic;
				ctrl_clock: in std_logic;
				ctrl_data_valid: out std_logic;
				slip_byte_in: in std_logic_vector(ram_data_width - 1 downto 0);
				slip_address_in: in std_logic_vector(ram_address_width - 1 downto 0);
				slip_write_in: in std_logic;
				ctrl_data_out: out std_logic_vector(ram_data_width - 1 downto 0);
				ctrl_address_in: in std_logic_vector(ram_address_width - 1 downto 0)
		);
end component slipbuffer;
-----
end package slip_pkg;