-------------------------------------------------- -- SLIP.vhd hh -- March 17, 2002 -- Steven Dytiuk, NETCON group -- -- Interfaces SLIP to RS232 protocol -- Uses the RS232 files from 2002 Student App Notes -- by Ben's group -- this file entity interface adapted from -- serialport.vhd -------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library work; use work.RS_232_In_Pkg.all; use work.RS_232_Out_Pkg.all; use work.slip_pkg.all; entity SLIP is generic ( TwoWords: positive := 19); -- 19 + 1 = 20 words is the size of two incoming RS232 words -- used for override on ESCape characters port ( clock: in std_logic; -- pin 91 @ 25.175 MHz soutclr: in std_logic; -- sync. clear for output reset: in std_logic; -- reset clock divider serialin: in std_logic; -- data stream IN serialout: out std_logic; -- data stream OUT serialinData: out std_logic_vector(bytesize - 1 downto 0); -- the data packet read in input_data_valid: out std_logic; -- indicates data is valid serialoutData: in std_logic_vector(bytesize - 1 downto 0); -- the data packet to send out out_load: in std_logic; -- pulse high to load the serialOutData and send it enableSerialout: in std_logic; -- serial out enable outReady: out std_logic; -- indicates we are ready to rx/load a new data word pktRead: out std_logic; -- pulses high when end is received slip_clock: out std_logic; slip_addr_out: out std_logic_vector(ram_address_width - 1 downto 0); out_finished: in std_logic; -- to send the END control char after packet done slip_write_out: out std_logic -- high when sending data to controller ); end SLIP; architecture mixed of SLIP is component clkdiv IS -- default to .75H -- 25.175 MHz/ (2**24) /2 generic (Divisor: positive :=33554432); -- clock division rate port(fast_clock : in STD_LOGIC; reset : in STD_LOGIC; slow_clock : buffer STD_LOGIC); END component clkdiv; --- signal to_send_data1, to_send_data2: std_logic_vector (7 downto 0); signal out_load_delay: std_logic; signal rx_data: std_logic_vector (7 downto 0); signal serial_input_clock, serial_output_clock, RX_Clock : std_logic; signal data_valid_delay: std_logic; signal escd_char: std_logic; signal addr_counter: std_logic_vector(ram_address_width - 1 downto 0); --- begin inclkdiv: clkdiv generic map( Divisor => inCLKDivisor ) port map( fast_clock => clock, reset => reset, slow_clock => serial_input_clock ); outclkdiv: clkdiv generic map( Divisor => outCLKDivisor ) port map( fast_clock => clock, reset => reset, slow_clock => serial_output_clock ); rxCLKDIV: clkdiv generic map( Divisor => RXCLKDivisor ) port map( fast_clock => clock, reset => reset, slow_clock => RX_Clock ); serialRX: RS_232_In port map( clock => serial_input_clock, shiftin => serialin, q => rx_data, data_valid => data_valid_delay ); serialTX: RS_232_Out port map( clock => serial_output_clock, enable => enableserialout, sset => soutclr, load => out_load_delay, data => to_send_data2, shiftout => serialout, ready => outready ); slip_clock <= RX_Clock; ---------------------- p1: process(serial_input_clock) -- for RECEIVING serial data variable b_endrxed: natural range 0 to 1 := 0; --variable addr_counter: natural range 0 to ram_data_size - 1 := 0; variable escd_char: natural range 0 to 1 := 0; begin if rising_edge(serial_input_clock) then if data_valid_delay = '1' then if escd_char = 0 then case rx_data is when ESC_char => b_endrxed := 1; escd_char := 1; serialindata <= Nothing_char; slip_write_out <= '0'; pktRead <= '0'; when END_char => -- slip transmitter should send end chars when line is empty -- or end_char followed by nothing_char's --serialindata <= Nothing_char; serialindata <= rx_data; if b_endrxed = 1 then pktRead <= '1'; b_endrxed := 0; else pktRead <= '0'; end if; slip_write_out <= '0'; addr_counter <= address_zero; when Nothing_char => serialindata <= Nothing_char; if b_endrxed = 1 then slip_addr_out <= addr_counter; slip_write_out <= '1'; addr_counter <= addr_counter + '1'; else slip_write_out <= '0'; end if; pktRead <= '0'; when others => serialindata <= rx_data; slip_addr_out <= addr_counter; slip_write_out <= '1'; b_endrxed := 1; addr_counter <= addr_counter + '1'; pktRead <= '0'; end case; else case rx_data is when ESC_END_char => serialindata <= END_char; when ESC_ESC_char => serialindata <= ESC_char; when others => serialindata <= rx_data; end case; slip_write_out <= '1'; slip_addr_out <= addr_counter; addr_counter <= addr_counter + '1'; escd_char := 0; pktRead <= '0'; end if; input_data_valid <= data_valid_delay; end if; end if; end process; ---------------------- p2: process(serial_output_clock) --to send data out variable count: natural range 0 to 19; variable end_count: natural range 0 to 10; variable end_loop: natural range 0 to 1; variable statetype: natural range 0 to 1; begin if rising_edge(serial_output_clock) then if ((out_finished = '1') or (end_loop = 1)) then to_send_data2 <= END_Char; end_loop := 1; if end_count = 0 then out_load_delay <= '1'; else out_load_delay <= '0'; end if; end_count := end_count + 1; if end_count = 10 then end_count := 0; end_loop := 0; count := 0; statetype := 0; end if; elsif statetype = 1 then if count = 9 then to_send_data2 <= to_send_data1; out_load_delay <= '1'; else out_load_delay <= '0'; end if; count := count + 1; if count = 19 then count := 0; statetype := 0; end if; else case serialoutdata is when END_char => statetype := 1; to_send_data2 <= ESC_char; to_send_data1 <= ESC_END_char; out_load_delay <= '1'; when ESC_char => statetype := 1; to_send_data2 <= ESC_char; to_send_data1 <= ESC_ESC_char; out_load_delay <= '1'; when others => to_send_data2 <= serialoutdata; out_load_delay <= out_load; end case; end if; end if; end process; end mixed;