Compiling in Quartus II

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Description

This app note describes some peculiarities in compiling designs with Quartus II. The version used at the time of writing was 1.1, although 2.0 has been released.

Designs with multiple files

As an example, say you are designing a 4-bit adder using several single bit adders. Your single bit adder file is called adder_1.vhd:

-- adder_1.vhd

library ieee;
use ieee.std_logic_1164.all;

entity adder_1 is

  port (
    a, b, cin   : in  std_logic;
    sum, cout   : out std_logic);

end entity adder_1;

architecture demo of adder_1 is

begin  -- architecture demo

  sum <= (a xor b) xor cin;
  cout <= (a and b) or (cin and a) or (cin and b);
  
end architecture demo;
 

And your top level file is called adder_4.vhd:

-- adder_4.vhd

library ieee;
use ieee.std_logic_1164.all;

entity adder_4 is
  
  port (
    a, b : in  std_logic_vector(3 downto 0);
    sum  : out std_logic_vector(3 downto 0);
    cin  : in  std_logic;
    cout : out std_logic);

end entity adder_4;

architecture demo of adder_4 is

  component adder_1
    
  port (
    a, b, cin   : in  std_logic;
    sum, cout   : out std_logic
    );

  end component adder_1;

  signal carries : std_logic_vector(3 downto 0);
  
begin  -- architecture demo

  
  adder_input_inst : adder_1
    port map (
      a    => a(0),
      b    => b(0),
      cin  => cin,
      cout => carries(0),
      sum  => sum(0));
  
  adders_inst: for i in 1 to 3 generate
  begin  -- generate adders_inst
    adder_1_inst : adder_1
      port map (
        a    => a(i),
        b    => b(i),
        cin  => carries(i-1),
        cout => carries(i),
        sum  => sum(i));
  end generate adders_inst;

end architecture demo;
 

In order to compile this design, open adder_4.vhd in Quartus and select "Processing->Set Compilation Focus to Current Entity" (or hit ctrl-J). Choose "Create New Project" when asked, and choose your working directory and top level design name and entity (i.e. adder_4). You can add other files to the project in the following page of the wizard, but it is important to note that you do not need to add adder_1.vhd to the project. As long as adder_1.vhd is in the working directory of the project, Quartus will find it automatically. Finish with the wizard, and Quartus will create a database directory and a project file in the directory you specified. Ensure that adder_1.vhd is in your project directory. Select "Processing->Compile" (or hit ctrl-L) to compile the design. Quartus will automatically compile adder_1.vhd, so there is no further need to compile all sub-components in a hierarchical design.

If your designs require a common package, things changes slightly. Say you want to specify a package adder_defs.vhd that contains some constants that you want both adder_1.vhd and adder_4.vhd to reference. Add the usual use work.adder_defs.all to the beginning of each file, and select "Project->Add Files to Project". Add adder_defs.vhd to the list of files. At this point it is important that adder_1.vhd is not included in the list of project files. If it is, Quartus will try to parse adder_defs.vhd twice: once for adder_1.vhd and again for adder_4.vhd. Declaring constants twice anywhere will cause an error, and this case is no exception, although Quartus won't tell you why.

Structural Files

Quartus will not let you slice a port like so:

  num_add_sub_1 : component lpm_add_sub
    generic map (
      LPM_WIDTH          => 16)
    port map (
      dataa(15 downto 8) => a_stg1_top,
      dataa(7 downto 0)  => a_stg1_bottom,
      datab              => b_stg1,
      aclr               => clear,
      add_sub            => num_add_sub_stg1,
      cout               => num_carry,
      overflow           => num_overflow_stg1,
      result             => num_stg1(15 downto 0)
      );
 

If you have a structural file and Quartus is giving you weird errors when you try to compile it, this may be your problem. Your ports can not be sliced. You have to either instantiate two components of the requisite width, or use one component like so:

  num_add_sub_1 : component lpm_add_sub
    generic map (
      LPM_WIDTH => 16)
    port map (
      dataa     => a_stg1,
      datab     => b_stg1,
      aclr      => clear,
      add_sub   => num_add_sub_stg1,
      cout      => num_carry,
      overflow  => num_overflow_stg1,
      result    => num_stg1(15 downto 0)
      );

Note, however, that you may slice signals connected to component ports.