------------------------------------------------- -- The package of tmc_ram -------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; library work; package tmc_ram_pkg is --constant data_width : positive :=16; --subtype datapath is std_logic_vector (data_width-1 downto 0); -- Adding adder as a component in the package Component tmc_ram is generic ( address_width : positive := 10; data_size : positive := 1024; ram_data_width : positive := 5 ); port ( indata_reg : in std_logic_vector ( ram_data_width - 1 downto 0 ); -- width of the input data with the ASCII code address : in std_logic_vector ( address_width - 1 downto 0 ); write_enable : in std_logic := '1'; -- enable to write data clock : in std_logic; -- system clock --outputen : out std_logic := '0'; ram_out : out std_logic_vector ( ram_data_width - 1 downto 0 ) ); end component tmc_ram; -- end of the component tmc_ram Component MsgCounter is Generic ( message_width : positive := 10; address_width : positive := 10; data_size : positive := 1024; ram_data_width : positive := 5 ); Port ( indata : in std_logic_vector ( ram_data_width - 1 downto 0 ); -- width of the input data with the ASCII code write_enable : in std_logic := '1'; -- enable to write data message_enable : in std_logic := '1'; -- enable to write message counter loaddata : in std_logic := '0'; -- enable the loading the data into the counter clock : in std_logic; -- system clock outputen : out std_logic := '1'; -- output data enable to indicate ready to receive signal reset : in std_logic := '0'; -- reset address counter ram_out : out std_logic_vector ( ram_data_width - 1 downto 0 ); message_count : out std_logic_vector(message_width-1 downto 0) ); end component MsgCounter; -- end of the component MsgCounter end package tmc_ram_pkg; -- end of the package