---------------------------------------------------------------
-- This unit is for a RAM which is called 
-- tmc_ram.vhd,  it is used to store one message which 
-- would have a maximum of 50 words.  50 messages maximum.
---------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lpm;
use lpm.lpm_components.all;


entity tmc_ram is

generic (
	
			address_width 	: positive 	:= 10;
			data_size 		: positive 	:= 1024; 
			ram_data_width 	: positive 	:= 5
	    );

port ( 
	    indata_reg  	 : in std_logic_vector ( ram_data_width - 1 downto 0 );     -- width of the input data with the ASCII code
        address		 : in std_logic_vector ( address_width - 1 downto 0 );
		write_enable : in std_logic := '1'; 		                            -- enable to write data
		clock 		 : in std_logic; 				                            -- system clock
		--outputen	: out std_logic := '0';
	    ram_out  	 : out std_logic_vector ( ram_data_width - 1 downto 0 )        
      );

end tmc_ram;

-- beginning of architecture of tmc
architecture structural of tmc_ram is

signal outdata_reg : std_logic_vector( ram_data_width - 1 downto 0 );

Begin

-- using the lpm_ram_dq to distribute the ram and determine the read or write status

ram_instance : COMPONENT lpm_ram_dq
	GENERIC MAP (
				  lpm_type 		=> 	"L_RAM_DQ",
			      lpm_width   	=> 	ram_data_width,                            -- width of the input and output data
        	      lpm_widthad 	=> 	address_width,                             -- width of the address
				  lpm_numwords 	=> 	data_size,                                 -- maximum number of data
				  lpm_indata 	=> 	"registered",
			      lpm_outdata 	=> 	"registered"                                          
				)

	PORT MAP ( 
			   data 	=> 	indata_reg,
			   we 		=> 	write_enable,                                      -- determine the status of read or write
			   address 	=> 	address,                                        -- address counter
		       inclock 	=> 	clock,                                             -- synchronized clock
			   outclock => 	clock,                                             -- synchronized clock
               q 		=> 	outdata_reg
			  );

-- for output register
	reg2: process (clock) 
	begin
		if rising_edge (clock) then
			ram_out <= outdata_reg;
		end if;
end process;

end structural;