---------------------------------------------------------------
-- This unit is for a number the message of the tmc_ram 
-- Counting from one to ten message
---------------------------------------------------------------
library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_arith.all;
Use IEEE.std_logic_unsigned.all;
library lpm;
Use lpm.lpm_components.all;
library work;
Use work.tmc_ram_pkg.all;

entity MsgCounter is

Generic (
			message_width	: positive  := 4;
			address_width	: positive	:= 10;
			data_size 		: positive 	:= 1024; 
			ram_data_width 	: positive 	:= 5
		);

Port ( 
		clock 			: in std_logic; 									   -- system clock
		indata    		: in std_logic_vector ( ram_data_width - 1 downto 0 ); -- width of the input data with the ASCII code
   		messagenum 		: in std_logic_vector ( message_width - 1 downto  0);
		readmessage		: in std_logic := '0';								   -- in read process
		receive_enable	: out std_logic := '1';
		write_enable 	: in std_logic := '0'; 								   -- in write process
		read_enable 	: in std_logic := '0';
								   -- from decompressoion
		outputen 		: buffer std_logic := '1'; 							   -- output data enable to indicate ready to receive signal
		message_done 	: out std_logic := '0';								   -- reset the message
		reset			: in std_logic := '0';   							   -- reset address counter
		ram_out 		: out std_logic_vector ( ram_data_width - 1 downto 0 )     
	     );

end MsgCounter;

-- beginning of architecture of tmc
architecture structural of MsgCounter is

signal messagecounter : std_logic_vector ( message_width - 1 downto 0 ) := "0000000001";  -- message counter
signal addcounter: std_logic_vector ( address_width - 1 downto 0 ) := ( others => '0' );      -- address coun
signal indata_reg : std_logic_vector( ram_data_width - 1 downto 0 );  -- for the input register
signal message_enable : std_logic := '0';
signal clk_enable : std_logic := '0';
type   state_type is ( ready, write, read, waiting, charaready, messageready, idle, searching );
signal state: state_type;
signal counter_enable : std_logic := '0';
signal resetaddress : std_logic := '0';
signal resetmessage : std_logic := '0';
signal outdata_reg		: std_logic_vector ( ram_data_width - 1 downto 0 );
--signal message_done : std_logic := '0';
signal message_temp : std_logic_vector ( message_width - 1 downto 0 );

Begin


-- using the lpm_counter to count the address for one message
message_counter : component lpm_counter
	GENERIC MAP (
				  lpm_width   => message_width,
        	      lpm_type 	  => "L_counter",
				  lpm_direction => "up"

				)
	PORT MAP ( 
		      data => messagecounter,
			  clock => message_enable,
			  sload => counter_enable,
              sclr => resetmessage,
			  q => messagecounter
			  );


address_counter : component lpm_counter
	GENERIC MAP (
				  lpm_width   => address_width,
        	      lpm_type => "L_counter",
				  lpm_direction => "up"
		 		)
	PORT MAP ( 
		      data => addcounter,
			  clock => counter_enable,
              --sload =>  counter_enable,
              sclr => resetaddress,
			  q => addcounter
			  );

message_temp <= messagenum - 1;
-- using the state machine for different state when 
machine : process ( clock )
begin
    if (reset = '1') then
		resetmessage <= '0';
		resetaddress <= '0';
	elsif rising_edge ( clock ) then
		case state is
			when ready =>
				receive_enable <= '1';
				if ( write_enable = '1' ) then
					state <= write;
				elsif ( readmessage = '1' ) then
					state <= read;
				end if;

			when write =>	
				counter_enable <= write_enable;
				outputen <= '0';
				state <= idle;
			
			when idle =>
				counter_enable <= write_enable;
				outputen <= '0';
				if ( write_enable = '1' ) then
					state <= write;
				elsif ( readmessage =  '1' ) then 
						state <= read;
			    end if;

			when read =>	
				resetaddress <= '1';
				resetmessage <= '1';
				counter_enable <= read_enable;
				if ( read_enable = '1') then
					receive_enable <= '0';
					ram_out <= "11111";
					state <= waiting;
	 			end if;

			when waiting =>	
				outputen <= '0';
				counter_enable <= '0';
				state <= searching;

		
			when searching =>
				resetaddress <= '0';
				resetmessage <= '0';
				if ( outdata_reg = "00000"  ) then
					message_enable <= '1';
				else
					message_enable <= '0';
				end if;
				counter_enable <= '1';

				if ( messagecounter = message_temp) then
				--	outputen <= '1';
					state <= messageready;
				else
					state <= waiting;
				end if;
			
		
			when messageready =>
					counter_enable <= '0';
				 	outputen <= '0';
					state <= charaready; 
					
		
			when charaready =>
			    counter_enable <= '1';
			    if ( outdata_reg = "00000"  ) then		-- check for the ending of the required message
					   message_done <= '1';				-- signal to team that done message 
				       outputen <= '0';
					   state <= idle;
				else									-- printing out each character to ram_out
					   message_done <= '0';
					   outputen <= '1';
					   ram_out <= outdata_reg;
					   
					   state <= messageready;
			    end if;

		end case;
end if;							

end process;

ram : component tmc_ram
	Generic Map (
			address_width 	 => address_width,
			data_size 		=> data_size, 
			ram_data_width 	=> ram_data_width
			)
	Port Map( 
		    indata_reg  => indata_reg, 	 
    	    address		 => addcounter,
			write_enable => write_enable,
			clock 		 => clock,
	    	ram_out  	 => outdata_reg
		      );

-- for input register			

reg1: process (clock) 
begin
	if rising_edge (clock) then
	   indata_reg <= indata;
	end if;
end process;

end structural;