--register

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity registerN is
    generic(N : positive := 8);
    port (	Input   : in std_logic_vector(N-1 downto 0);
          	Load  	: in std_logic;
			Clock	: in std_logic;
	  		Reset	: in std_logic;
          	Output  : out std_logic_vector(N-1 downto 0));
end registerN;

-- structural implementation of the N-bit adder
architecture behavioural of registerN is

begin

	process(Reset, Clock)
	begin
		if(Reset = '0') then 
			Output <= (others => '0');
		elsif Clock = '1' and Clock'event then
			if (Load = '1') then
				Output <= Input;
			end if;
		end if;
	end process;

end behavioural;