--This component controls the length over which
--The load signal is high
--Entity Name is load_control.Vhd

library ieee;
use ieee.std_logic_1164.all;

library work;
use work.code_pkg.all;

Entity load_control is 
	Port
	(	
		Signal_in 	: IN std_logic;
		Clk 		: IN std_logic;
		load_length : IN std_logic_vector(3 downto 0);
--Load length=> # of cycles that load signal is High
		load_signal : OUT std_logic
);
End Entity Load_control;

Architecture Behavioral of load_control is
signal delay_sig1 : std_logic;
signal and_out : std_logic;
BEGIN
 Process(Clk,Signal_in)
BEGIN
	and_out <= delay_sig1 and signal_in;
	load_signal <= 	and_out xor signal_in;
END Process;
delay_sig : component delay port map(signal_in,load_length,clk,delay_sig1);
END Behavioral;