-- Entity name interface.vhd
-- This VHDL gets input from the Glove and processes to VGA or 
-- Seven segment Display.
-- HGH => hand held glove 

library ieee;
use ieee.std_logic_1164.all;
library work;
use work.code_pkg.all;

entity interface is
port
(
	hgh_data_in : IN std_logic_vector(4 downto 0);
	reset 		: IN std_logic;
	clk 		: IN std_logic;
	--external_enable : IN std_logic;
--	dat_out_test : OUT std_logic_vector(7 downto 0);
	ps_enable	: OUT std_logic;
	vga_enable	: OUT std_logic;
	data_out	: OUT std_logic_vector(4 downto 0);
	Ascii_out	: OUT std_logic_vector(7 downto 0)
	);
end entity interface;

architecture RTL of interface is
signal nor_out : std_logic;
signal nor_debounced : std_logic;
signal sr_reset : std_logic;
signal load_reg : std_logic;
signal load_reg_delay : std_logic_vector(3 downto 0);
signal load_reg_delayed : std_logic;
signal sr_delay : std_logic_vector(3 downto 0);
signal load_reg_active : std_logic_vector(3 downto 0);
signal ps_load_active : std_logic_vector(3 downto 0);
signal vga_load_active : std_logic_vector(3 downto 0);
signal sr_out : std_logic_vector(4 downto 0);
signal register_out : std_logic_vector(4 downto 0);
signal internal_data_in : std_logic_vector (4 downto 0);
signal debounced_data_in : std_logic_vector (4 downto 0);
signal Ascii_out_test : std_logic_vector (7 downto 0);
begin
	process(hgh_data_in,clk)
		begin
			load_reg_delay <= "0111"; 
--clock delay for the register load signal that ps/2 and VGA load valid data
			sr_delay <= "1111";
			load_reg_active <= "1111";
			ps_load_active  <= "0100";
			vga_load_active <= "0100";
			internal_data_in <= not hgh_data_in;
			--if external_enable = '1' then
			--dat_out_test <= Ascii_out_test;
			--end if;
			
	end process;
Activate_control_signal: component norN port map(internal_data_in ,nor_out);
DEBOUNCE: COMPONENT debouncer port map (nor_out,nor_debounced,clk);
signal_0_debounce : COMPONENT debouncer port map (internal_data_in(0),debounced_data_in(0),clk);
signal_1_debounce : COMPONENT debouncer port map (internal_data_in(1),debounced_data_in(1),clk);
signal_2_debounce : COMPONENT debouncer port map (internal_data_in(2),debounced_data_in(2),clk);
signal_3_debounce : COMPONENT debouncer port map (internal_data_in(3),debounced_data_in(3),clk);
signal_4_debounce : COMPONENT debouncer port map (internal_data_in(4),debounced_data_in(4),clk);
Delay_sr_reset: component delay port map(nor_debounced,sr_delay,clk,sr_reset);
Load_Activate : component load_control port map(nor_debounced,clk,load_reg_active,load_reg);
Latch_IO :	component S_R_latch port map(debounced_data_in,sr_out,sr_reset);
--load signal into the register uses a delayed sr_reset signal
--load signal into the register uses a delayed sr_reset signal
Register_IO: component registerN port map(sr_out,load_reg,Reset,register_out);
Delay_load_reg: component delay port map(load_reg,load_reg_delay,clk,load_reg_delayed);
Ascii_decode: component Ascii_decoder port map(register_out,load_reg,Ascii_out_test);
Ascii_out <= Ascii_out_test;
Ps_Load_Activate : component load_control port map(load_reg_delayed,clk,ps_load_active,ps_enable);
VGA_load_Activate : component load_control port map(load_reg_delayed,clk,VGA_load_active,VGA_enable);
data_out <= register_out;
end RTL;