------------------------------------------------- ------------------------------------------------- -- EE552 ASL and Handheld keyboard developement VHDL Code -- This Package will be used to store all components that --will be used for the final data path -- code_pkg.vhd library ieee; use ieee.std_logic_1164.all; package code_pkg is -------------------------------------------------------- --norN or gate component Component norN is port ( input : IN std_logic_vector(4 downto 0); output : OUT std_logic ); END component norN; --------------------------------------------------------- --five bit RS latch component S_R_latch is generic ( N: integer :=5); port( Set : in std_logic_vector(N-1 downto 0); output : out std_logic_vector (N-1 downto 0); Reset : in std_logic); end component S_R_latch; --------------------------------------------------------- --Five bit register component registerN is generic(N : positive := 5); port ( Input : in std_logic_vector(N-1 downto 0); Load : in std_logic; Reset : in std_logic; Output : out std_logic_vector(N-1 downto 0)); end component registerN; --------------------------------------------------------- -- ASCII decoder component Ascii_decoder is PORT ( --interface in is valid data recieved from the glove interface_in : IN std_logic_vector(4 downto 0); enable: IN std_logic; Ascii_data_out : OUT std_logic_vector(7 downto 0)); end component Ascii_decoder; ---------------------------------------------------------- --led_decoder component led_decoder is port ( --interface in is valid data recieved from the glove interface_in : IN std_logic_vector(4 downto 0); enable: IN std_logic; led_data_out : OUT std_logic_vector(7 downto 0)); end component led_decoder; --------------------------------------------------------- component hex_display is PORT ( --interface in is valid data recieved from the glove led_data : IN std_logic_vector(7 downto 0); enable : IN std_logic; led_a : OUT std_logic_vector(7 downto 0); led_b : OUT std_logic_vector(7 downto 0)); end component hex_display; ---------------------------------------------------------- Component debouncer is PORT( INPUT : IN std_logic; OUTPUT : OUT std_logic; CLOCK : IN std_logic ); END COMPONENT debouncer; ---------------------------------------------------------- component delay is port ( signal_in : in std_logic; cycles : in std_logic_vector(3 downto 0); clk: in std_logic; delayed_sig : out std_logic ); end component delay; ---------------------------------------------------------- Component load_control is Port ( Signal_in : IN std_logic; Clk : IN std_logic; load_length : IN std_logic_vector(3 downto 0); --Load length=> # of cycles that load signal is High load_signal : OUT std_logic ); End Component Load_control; ---------------------------------------------------------- end package code_pkg;