-- Five input
-- S_R_latch

library ieee;
use ieee.std_logic_1164.all;

entity S_R_latch is
--generic ( N: integer :=5);
port( 	Set : in std_logic_vector(4 downto 0);
		output : out std_logic_vector (4 downto 0);
		Reset : in std_logic); 
end S_R_latch;

architecture behavioral of S_R_latch is
--constant width : integer := 5;
--signal output : std_logic_vector (width-1 downto 0);

begin

Process (Set, Reset) 
begin
	
		case Set(0) is
			when '1' => 
				output(0) <= '1';
			when others =>
				null;
		end case;
		case Set(1) is
			when '1' => 
				output(1) <= '1';
			when others =>
				null;
		end case;

		case Set(2) is
			when '1' => 
				output(2) <= '1';
			when others =>
				null;
		end case;

		case Set(3) is
			when '1' => 
				output(3) <= '1';
			when others =>
				null;
		end case;

		case Set(4) is
			when '1' => 
				output(4) <= '1';
			when others =>
				null;
				end case;


		case Reset is
			when '1' =>
				output <= "00000";
			when others =>
				null;
		end case;
	
--four is the width of the parrallel SR latch
		
			
end process;

end behavioral;