-- pipelined signal distance finder.  two pipeline registers are
-- inserted after the 3 bits and 4 bits incomplete adder; 
-- total logic cells : 178; min. clock period 22.1ns

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.CDMA_pkg.all;

entity pipelinedmeter is
        generic (width : positive := 32);
        port (
                resetn         : in  std_logic;
                clock         : in  std_logic;
                weight_vector : in  std_logic_vector(width -1 downto 0);
                distance      : out std_logic_vector(5 downto 0)
        );
end pipelinedmeter;

architecture mixed of pipelinedmeter is

  signal ones,zeros : std_logic;
  signal x : std_logic_vector(113 downto 0);
  signal y : std_logic_vector(87 downto 0);

begin  -- mixed

        ones <='1';
        zeros<='0';
  
        -- the bits are xor 'ed in pairs;
        first_stage: for i in 0 to width/2 -1 generate
                constant index0 : positive := 2*i;
                constant index1 : positive := 2*i+1;
        begin
                first_stage: half_adder
                        port map (
                                a => x(index0),
                                b => x(index1),
                                c => y(index1),
                                s => y(index0)
                        );
        end generate first_stage;
    
        reg : latchreg 
        generic map (width => 32)
        port map (
                clock        => clock,
                resetn       => resetn,
                enable       => ones,
                parallel_in  => y(31 downto 0),
                parallel_out => x(63 downto 32)
        );

        -- every two bits are operated like they are summed;
        sums: for i in 1 to 4 generate
        begin

        con1: if i = 1 generate
                        constant stage_x_start : positive := 32;
                        constant stage_y_start : positive := 32;
                        constant adder_size : positive := 2;
                        constant adder_queue : positive := 8;
                begin

                adderqueue1: for j in 0 to adder_queue-1 generate
                    constant blocks : positive := adder_size+1;
                begin
                    adderi : adderinc
                    generic map (width => adder_size)
                    port map
                    (adden1 => x(stage_x_start+(2*j+1)*adder_size-1 downto
                                 stage_x_start+ 2*j*adder_size),
                     adden2 => x(stage_x_start+2*(j+1)*adder_size-1 downto
                                 stage_x_start + (2*j+1)*adder_size),
                     sum    => y(stage_y_start+(j+1)*blocks-1 downto
                                 stage_y_start+j*blocks)
                     );
                end generate adderqueue1;

                reg : latchreg
                     generic map (width => 24)
                     port map (
                     clock        => clock,
                     resetn       => resetn,
                     enable       => ones,
                     parallel_in  => y(55 downto 32),
                     parallel_out => x(87 downto 64)
                     );
                end generate con1;
    
        con2: if i=2 generate
                        constant stage_x_start : positive := 64;
                        constant stage_y_start : positive := 56;
                        constant adder_size : positive := 3;
                        constant adder_queue : positive := 4;      
                begin

                adderqueue2: for j in 0 to adder_queue-1 generate
                         constant blocks : positive := adder_size+1;
                 begin
                       adderi : adderinc
                       generic map (width => adder_size)
                       port map (
                       adden1 => x(stage_x_start+(2*j+1)*adder_size-1 downto 
                                   stage_x_start+ 2*j*adder_size),
                       adden2 => x(stage_x_start+2*(j+1)*adder_size-1 downto
                                   stage_x_start + (2*j+1)*adder_size),
                       sum    => y(stage_y_start+(j+1)*blocks-1 downto
                                   stage_y_start+j*blocks)
                                );
                        end generate adderqueue2;

                -- insert pipeline regsiter;
                reg : latchreg 
                        generic map (width => 16)
                        port map (
                                clock        => clock,
                                resetn       => resetn,
                                enable       => ones,
                                parallel_in  => y(71 downto 56),
                                parallel_out => x(103 downto 88)
                        );
                end generate con2;
    
        con3: if i=3 generate
                        constant stage_x_start : positive := 88;
                        constant stage_y_start : positive := 72;
                        constant adder_size : positive := 4;
                        constant adder_queue : positive := 2;      
                begin
                adderqueue3: for j in 0 to adder_queue-1 generate
                        constant blocks : positive := adder_size+1;
                        begin
                        adderi : adderinc 
                        generic map (width => adder_size)
                        port map (
                        adden1 => x(stage_x_start+(2*j+1)*adder_size-1 downto
                                    stage_x_start+ 2*j*adder_size),
                        adden2 => x(stage_x_start+2*(j+1)*adder_size-1 downto
                                    stage_x_start + (2*j+1)*adder_size),
                        sum    => y(stage_y_start+(j+1)*blocks-1 downto
                                    stage_y_start+j*blocks)
                                );
                        end generate adderqueue3;

                --insert pipeline register
                reg : latchreg 
                        generic map (width => 10)
                        port map (
                                clock        => clock,
                                resetn       => resetn,
                                enable       => ones,
                                parallel_in  => y(81 downto 72),
                                parallel_out => x(113 downto 104)
                        );

                end generate con3;
    
        con4: if i=4 generate
                        constant stage_x_start : positive := 104;
                        constant stage_y_start : positive := 82;
                        constant adder_size : positive := 5;
                        constant adder_queue : positive := 1;      
                begin

                adderqueue4: for j in 0 to adder_queue-1 generate
                        constant blocks : positive := adder_size+1;
                        begin
                        adderi : adderinc 
                        generic map (width => adder_size)
                        port map (
                        adden1 => x(stage_x_start+(2*j+1)*adder_size-1 downto
                                    stage_x_start+ 2*j*adder_size),
                        adden2 => x(stage_x_start+2*(j+1)*adder_size-1 downto
                                    stage_x_start + (2*j+1)*adder_size),
                        sum    => y(stage_y_start+(j+1)*blocks-1 downto
                                    stage_y_start+j*blocks)
                                );
                        end generate adderqueue4;        

                end generate con4;
    
        end generate sums;
        x(31 downto 0) <= weight_vector;
        distance <= y(87 downto 82);
  
end mixed;