Clock Stretcher
 
Author: David Munroe
Group: SysFX
 
On occasion, a slower clock is needed to run certain portions of project. The following code operates on the formula included and performs the following functions:
 
             1. Streches clock pulse by even multiple of original clock signal
             2. Allows for synchronous operation of different components at different clock speeds.
 

-- Changes the period of a master clock according to:
--          2 * numpulses * Period1 = Period2
--          unless numpulses = 0, in which case Period1 = Period2

library ieee;
use ieee.std_logic_1164.all;

package clock_pkg is

component clock_mult is
      generic ( numpulses : integer);
      port ( master_clock : in std_logic;
            changed_clock : out std_logic);
end component clock_mult;

end clock_pkg;


library ieee;
use ieee.std_logic_1164.all;

library work;
use work.clock_pkg.all;

entity clock_mult is
      generic (numpulses : positive := 1);
      port ( master_clock, reset : in std_logic;
                  changed_clock : out std_logic);
end entity clock_mult;


architecture pulse_div of clock_mult is
signal curr_clock : std_logic;

begin

clk_mult: process(master_clock, reset)

variable count : integer range 0 to numpulses - 1;

begin
      if numpulses = 0 then
            changed_clock <= master_clock;
      elsif rising_edge(master_clock) then
            if count = numpulses - 1 then
                  curr_clock <= not curr_clock;
                  changed_clock <= curr_clock;
            end if;
            count := count + 1;
            if count > numpulses - 1 then
                  count := 0;
            end if;
      end if;

end process clk_mult;

end architecture pulse_div;