HOW TO MIMIC PS/2 MOUSE DATA TRANSMISSION WITH FPGA

PS/2 Protocol Bi-directionality

PS/2 serial asynchronous communication utilizes two bi-directional signals between the mouse and PC: clock and data.

(At the computer)

Pin	Name	Dir	Description
1	DATA	IN/OUT	Key Data
2	n/c	-	Not connected
3	GND	------	Ground
4	VCC	OUT	Power , +5 VDC
5	CLK	OUT	Clock
6	n/c	-	Not connected

These open-drain signals are normally pulled high by a pull-up resistor in the PC. The PC is the master in this relationship by governing communication to be in one of three possible states:

Bus State	Description
Idle	Both the clock and data lines are allowed to float high. During this state, the mouse is free to transmit data packets to the computer when set.
Inhibit	The clock is held low by the host. During this state, the Spatial Mouse cannot transmit data packets to the host.
Request to Send	The data line is held low and the clock is allowed to float high. During this state, the Spatial Mouse must get ready to receive commands from the host.

The mouse is the slave as it constantly has to monitor these states by reading from the clock and data buses. In addition to having to abide by these states, the mouse has to generate the clock required to send and receive data when necessary.

PS/2 Protocol Data Format

Mouse movement and button click commands come in the form of three consecutively transmitted data bytes. The first byte contains information about the directions of movement and whether either of the buttons are depressed. The remaining two bytes convey the magnitude of movement in either dimension.

PS/2 Timing Requirements

The communication between the host computer and mouse is handled through 11 bit packets. Each communication packet includes a start bit, the 8-bit data payload, an odd parity bit and a stop bit.

Bit 1	Bit 2	Bit 3	Bit 4	Bit 5	Bit 6	Bit 7	Bit 8	Bit 9	Bit 10	Bit11
Start bit 0	Data bit 0 LSB	Data bit 1	Data bit 2	Data bit 3	Data bit 4	Data bit 5	Data bit 6	Data bit 7 MSB	Odd Parity Bit	Stop Bit 1

Data transmission from mouse to PC can only take place in the idle state (when the clock and data lines are floating high). The mouse initiates transmission by firstly pulling the data line low (this is effectively the start bit) and secondly pulling the clock low for its first cycle of 11 clock pulses. After ten clock cycles and 10 transmitted data bits, the mouse allows the data bus to float high (this is effectively the stop bit) past the duration of the 11^th clock pulse. The following figure illustrates the timing restrictions for the PS/2 protocol.

TIMING PARAMETER DESCRIPTION MIN. TIME MAX. TIME

t1 DURATION OF CLK LOW 30 µSEC 50 µSEC

t2 DURATION OF CLK HIGH 30 µSEC 50 µSEC

t3 VALID DATA BEFORE FALLING EDGE OF CLOCK 5 µSEC

t3 VALID DATA AFTER RISING EDGE OF CLOCK 5 µSEC

The t1 and t2 parameters are just half clock periods. The t3 parameter can be thought of as data set-up time before the falling edge of a clock pulse and the t4 parameter can be thought of as data hold time after the rising edge of a clock pulse.

Meeting the PS/2 Timing Requirements (t1, t2, t3, & t4 shown in the above figure)

The t1 and t2 parameters are simply met by using a 12.5 KHz (80us) clock. Parameters t3 and t4 are guaranteed to be satisfied if a new data bit is only asserted a ¼ period after each rising edge of the clock. This can be done by triggering data off the rising edge of a clock that is ¼ period out of phase with the clock used for transmission. From this point on, the transmission clock asserted onto the data bus will be called “PC clock” and the data triggering clock will be called “Data clock”. The following figure illustrates the timing relationships between the PC clock, Data clock, and transmitted data.

The PC clock and Data clock can be easily generated by simultaneously clocking a rising-edge triggered flip-flop and falling-edge triggered flip-flop with a 25.0KHz clock.

The following figure illustrates the PC clock and Data clock generated from the above circuit and the data to be triggered by the Data clock.

Given that the PC clock and Data clock are correctly generated (with that exact phase relation), a byte can be transmitted with a shift-out register as well as a state machine as depicted in the following figure.

Tx_shift_register

The Tx_shift_register is an 11-bit shift register with parallel loading. When load is asserted high, the register is parallel loaded at port d with 11 bits (1 PS/2 packet). When shift is pulsed, one bit is outputted at port q on the pulse’s rising edge while enable_shift must be maintained high for any shifting to take place.

The shift_out_register component is described behaviorally. Initially the load signal is asserted high to load the register with input at port d so that the index value of the 11 bit wide input is set to zero pointing to the least significant bit. An internal 11 bit wide variable is used to hold the incoming data so that the data is not lost. Then once the register detects a rising edge of the shift signal it checks if the register has been enabled. If the “shift enable” signal is high, then the register proceeds to shift out one bit at a time starting at bit(0). After each shift, the index counter for the input data is incremented by one so that successive bits can be outputted.

Transmit Controller

A state machine is required to implement proper initiation and termination, as well as the correct number of bits transmitted is represented in the following state diagram for the transmit_controller.

The transmit_controller is advanced on the rising edges of the 25KHz system clock but also needs to look at the 12.5 KHz data_clock to ensure proper initiation of data transmission. Transmission of an entire byte requires that the Tx_enable is asserted high for the entire duration byte transmission. In the start state, the controller disables shifting in the Tx_shift_register and does not allow a clock to be driven onto the PC-mouse clock bus. The controller remains in the start state until Tx_enable is asserted high. When transmission is enabled, the controller moves into the load_data state where it sends a pulse to the Tx_shift_register to load next byte packet. While in this state, the controller checks the data_clock. If data_clock is low, the controller advances to the enable_shift state on the next system clock pulse, but if the data_clock is high, the controller will stall in the load_data state for one more system clock period. This timing maneuver ensures that the start bit will be asserted before the PC-mouse clock bus is dropped low from its floating high. In the enable_shift state, the controller starts asserting a high on enable_shift of the Tx_shift_register making it sensitive to the data_clock shift signal. Before the next state is reached, the start bit will have been asserted on the PC-mouse data bus. On the next system clock pulse, the controller advances to the drive_PC_clock state where starts enabling PC_clock to write onto the PC-mouse clock bus. Before the next state is reached, the PC_clock will have driven the PC-mouse clock bus low for the first time. The controller next enters the shift state where it remains in this state until all 11 bits have be transmitted. A counter (shift_count) that increments on each state advance indicates to the controller when to enter the stop state. In the stop state, the shift_enable and data_clock are deactivated and a done signal goes high to signify to a higher level entity that the byte transmission is complete.