-- Mazebot Project
-- EE552 Fall 2000
--
-- Authors:
-- Steve Dillen 225760
-- Farrah Rashid 354698
--
-- October 9, 2000
--
-- synchronizer.vhd
-- This file implements a synchronization circuit (adds flip flops to asynchronous input, 
-- thus eliminating glitches from being entered) for the inputs.  The user can specify how 
-- many stages of synchronization (32 max).
-- 

-- Include the standard logic types.
--
library ieee;
use ieee.std_logic_1164.all;

-- Define the synchronizer with a default level of 2.
--
entity synchronizer is

  generic( numberOfLevels : positive := 2 );

  port   ( clock        : in  std_logic;
           reset        : in  std_logic;
           input        : in  std_logic;
           output       : out std_logic
         );

end synchronizer;

architecture RTL of synchronizer is

  -- Identify the flip flop component used for the synchronizer
  --

  component dff

    port    (
              d    : in  std_logic;
              clk  : in  std_logic;
              clrn : in  std_logic;
              prn  : in  std_logic;
              q    : out std_logic 
            );

  end component dff;

  -- Identify internal signals used for the synchronizer
  --
  signal internal_input : std_logic_vector( numberOfLevels downto 0 );
  signal one_signal     : std_logic;
  signal resetn         : std_logic;

begin

  -- Hard-wired one signal
  --
  one_signal <= '1';

  -- Invert the reset to get an active low reset
  --
  resetn <= not reset;

  -- Setup the hard-wired connections for the initial input and
  -- final output
  --
  internal_input( 0 ) <= input;
  output              <= internal_input( numberOfLevels );

  -- Generate the synchronization circuit over the number of levels
  --
  synchronize_circuit : for index in numberOfLevels - 1 downto 0 generate

    -- Generate a D flip flop for each level
    --
    synchronizing_flop : dff port map (
                                        d    => internal_input( index ),
                                        clk  => clock,
                                        clrn => resetn,
                                        prn  => one_signal,
                                        q    => internal_input( index + 1 )
                                      );

  end generate;

end RTL;