Synchronizer in VHDL
by
Farrah Rashid
Steven Dillen
from the
MazeBot Team
Design
The main purpose of the synchronizer is to eliminate glitches caused by:
To remove the glitches, the synchronizer takes the given input signal and runs it through a specified number of flip flops. The synchronizer can also be used to wait for a specific number of clock cycles before sending out an input, useful in pipelining a valid signal. This is achieved by setting the numberOfLevels (see entity definition) to the number of clock cycles that you wish to wait.
The synchronizer instantiates the specified number of D flip flops using a generate command. It is important to note that the reset signal is active high. Maximum speed = 125 MHz
Links
Authors : Steven Dillen and Farrah Rashid
Team : Mazebot