--------------------------------------------
-- EE552 project: Image Indexing Processor
-- file name: query_rams.vhd
-- This file is used to implement a piece of
-- ram in EAB. This ram block will be used
-- to store the query image histogram with
-- R, G and B seperately.
--------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;

entity query_rams is
		port (clock: in std_logic;

--		input output for query_ram
		data_query_r: in std_logic_vector(15 downto 0);
		data_query_g: in std_logic_vector(15 downto 0);
		data_query_b: in std_logic_vector(15 downto 0);
		we_query: in std_logic;
		add_query_r: in std_logic_vector(3 downto 0); 
		add_query_g: in std_logic_vector(3 downto 0); 
		add_query_b: in std_logic_vector(3 downto 0); 
		q_query_r: out std_logic_vector(15 downto 0);
		q_query_g: out std_logic_vector(15 downto 0);
		q_query_b: out std_logic_vector(15 downto 0)
		);
end query_rams;

architecture structure of query_rams is
begin

query_r_ram:lpm_ram_dq
	GENERIC MAP ( 
		lpm_width			=>16,-- width of input and output data
		lpm_widthad			=>4, -- width of address
		lpm_indata			=>"REGISTERED", --registered for synchronous use
		lpm_outdata			=>"REGISTERED", --registered for synchronous use
		lpm_numwords		=>16,	-- maximum number of data
		lpm_address_control	=>"UNREGISTERED")
	PORT MAP (							--signals on the ports
		data				=>data_query_r,	
		we					=>we_query,	-- determines write or read
		address				=>add_query_r,-- address counter
		inclock				=>clock,	-- synchronized with system clock
		outclock			=>clock, 
		q					=>q_query_r);	-- output data
query_g_ram:lpm_ram_dq
	GENERIC MAP ( 
		lpm_width			=>16,-- width of input and output data
		lpm_widthad			=>4, -- width of address
		lpm_indata			=>"REGISTERED", --registered for synchronous use
		lpm_outdata			=>"REGISTERED", --registered for synchronous use
		lpm_numwords		=>16,	-- maximum number of data
		lpm_address_control	=>"UNREGISTERED")
	PORT MAP (							--signals on the ports
		data				=>data_query_g,	
		we					=>we_query,	-- determines write or read
		address				=>add_query_g,-- address counter
		inclock				=>clock,	-- synchronized with system clock
		outclock			=>clock, 
		q					=>q_query_g);	-- output data
query_b_ram:lpm_ram_dq
	GENERIC MAP ( 
		lpm_width			=>16,-- width of input and output data
		lpm_widthad			=>4, -- width of address
		lpm_indata			=>"REGISTERED", --registered for synchronous use
		lpm_outdata			=>"REGISTERED", --registered for synchronous use
		lpm_numwords		=>16,	-- maximum number of data
		lpm_address_control	=>"UNREGISTERED")
	PORT MAP (							--signals on the ports
		data				=>data_query_b,	
		we					=>we_query,	-- determines write or read
		address				=>add_query_b,-- address counter
		inclock				=>clock,	-- synchronized with system clock
		outclock			=>clock, 
		q					=>q_query_b);	-- output data

end structure;