-------------------------------------------------
-- EE552 project
-- file name: EAB_rams1.vhd
-- This file is used to implement 2 pieces of
-- ram in EABs. These ram blocks will be used
-- to store the query image histogram, candidate
-- image histogram. The names of these two ram
-- blocks are query_ram and cand_ram. 
-- The total EABS used are 4/6, 0 logic cell used.
--------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;

entity EAB_rams1 is
	
		port (clock: in std_logic;

--		input output for query_ram
		data_query: in std_logic_vector(15 downto 0);
		we_query: in std_logic;
		add_query: in std_logic_vector(5 downto 0); -- 48 address lines
		q_query: out std_logic_vector(15 downto 0);

--		input output for cand_ram
		data_cand: in std_logic_vector(15 downto 0);
		we_cand: in std_logic;
		add_cand: in std_logic_vector(5 downto 0);  -- 48 address lines
		q_cand: out std_logic_vector(15 downto 0)

		);

end EAB_rams1;

architecture structure of EAB_rams1 is
begin

query_ram:lpm_ram_dq
	GENERIC MAP ( 
		lpm_width		=>16,-- width of input and output data
		lpm_widthad		=>6, -- width of address
		lpm_indata		=>"REGISTERED",--registered for synchronous use
		lpm_outdata		=>"REGISTERED",--registered for synchronous use
		lpm_numwords	=>48,-- maximum number of data
		lpm_file		=>"init_query.mif", 
		lpm_address_control=>"UNREGISTERED")
	PORT MAP (			--signals on the ports
		data			=>data_query,	
		we				=>we_query,	-- determines write or read
		address			=>add_query,-- address counter
		inclock			=>clock,-- synchronized with system clock
		outclock		=>clock, 
		q				=>q_query);-- output data

cand_ram:lpm_ram_dq
	GENERIC MAP(
		lpm_width		=>16,-- width of input and output data
		lpm_widthad		=>6, -- width of address
		lpm_indata		=>"REGISTERED", --registered for synchronous use
		lpm_outdata		=> "REGISTERED",--registered for synchronous use
		lpm_numwords	=>48,-- maximum number of data
		lpm_file		=>"init_cand.mif",
		lpm_address_control	=>"UNREGISTERED")
	PORT MAP(			--signals on the ports
		data			=>data_cand,	
		we				=>we_cand, -- determines write or read
		address			=>add_cand,-- address counter
		inclock			=>clock,-- synchronized with system clock
		outclock		=>clock, 
		q				=>q_cand-- output data
		);
end structure;