-- file name: EAB_rams.vhd
-- This file is used to implement 4 piece of
-- ram in EAB. These ram blocks will be used
-- to store the query image histogram, candidate
-- image histogram, distance of all candidate 
-- image histograms to query image histogram, and 
-- the rank of candidate images. The name of this 
-- four ram block are query_ram, cand_ram, dist_ram
-- and rank_ram. 


library ieee;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;

entity EAB_rams is
	
		port (clock: in std_logic;

--		input output for query_ram
		data_query: in std_logic_vector(15 downto 0);
		we_query: in std_logic;
		add_query: in std_logic_vector(5 downto 0); -- 48 address lines
		q_query: out std_logic_vector(15 downto 0);

--		input output for cand_ram
		data_cand: in std_logic_vector(15 downto 0);
		we_cand: in std_logic;
		add_cand: in std_logic_vector(5 downto 0);  -- 48 address lines
		q_cand: out std_logic_vector(15 downto 0);

--		input output for dist_ram
		data_dist: in std_logic_vector(15 downto 0);
		we_dist: in std_logic;
		add_dist: in std_logic_vector(5 downto 0); -- 64 add lines for max 64 images
		q_dist: out std_logic_vector(15 downto 0)

--		input output for rank_ram
--		data_rank: in std_logic_vector(5 downto 0); -- max 64 images
--		we_rank: in std_logic;
--		add_rank: in std_logic_vector(3 downto 0);  -- top 10 most similar images
--		q_rank: out std_logic_vector(5 downto 0)
		);

end EAB_rams;

architecture structure of EAB_rams is
begin
		

query_ram:lpm_ram_dq
	GENERIC MAP ( 
		lpm_width			=>16,-- width of input and output data
		lpm_widthad			=>6, -- width of address
		lpm_indata			=>"REGISTERED", --registered for synchronous use
		lpm_outdata			=>"REGISTERED", --registered for synchronous use
		lpm_numwords		=>48,	-- maximum number of data
		lpm_address_control	=>"UNREGISTERED")
	PORT MAP (							--signals on the ports
		data				=>data_query,	
		we					=>we_query,	-- determines write or read
		address				=>add_query,-- address counter
		inclock				=>clock,	-- synchronized with system clock
		outclock			=>clock, 
		q					=>q_query);	-- output data

cand_ram:lpm_ram_dq
	GENERIC MAP(
		lpm_width			=>16,-- width of input and output data
		lpm_widthad			=>6, -- width of address
		lpm_indata			=>"REGISTERED", --registered for synchronous use
		lpm_outdata			=> "REGISTERED",--registered for synchronous use
		lpm_numwords		=>48,	-- maximum number of data
		lpm_address_control	=> "UNREGISTERED")
	PORT MAP(						--signals on the ports
		data				=>data_cand,	
		we					=>we_cand, -- determines write or read
		address				=>add_cand,-- address counter
		inclock				=>clock,-- synchronized with system clock
		outclock			=>clock, 
		q					=>q_cand);-- output data

dist_ram:lpm_ram_dq
	GENERIC MAP ( 
		lpm_width			=>16,	-- width of input and output data
		lpm_widthad			=>6,	-- width of address
		lpm_indata			=>"REGISTERED", --registered for synchronous use
		lpm_outdata			=>"REGISTERED", --registered for synchronous use
		lpm_numwords		=>64,			--maximum number of data
		lpm_address_control	=>"UNREGISTERED")
	PORT MAP (							--signals on the ports
		data				=>data_dist,	
		we					=>we_dist,-- determines write or read
		address				=>add_dist,-- address counter
		inclock				=>clock,-- synchronized with system clock
		outclock			=>clock, 
		q					=>q_dist);-- output data

--rank_ram: lpm_ram_dq
--	GENERIC MAP ( 
--		lpm_width			=>6,-- width of input and output data
--		lpm_widthad			=>4,-- width of address
--		lpm_indata			=>"REGISTERED",--registered for synchronous use
--		lpm_outdata			=>"REGISTERED", --registered for synchronous use
--		lpm_numwords		=>10,-- maximum number of data
--		lpm_address_control	=>"UNREGISTERED")
--	PORT MAP (					--signals on the ports
--		data				=>data_rank,	
--		we					=>we_rank,-- determines write or read
--		address				=>add_rank,-- address counter
--		inclock				=>clock,-- synchronized with system clock
--		outclock			=>clock, 
--		q					=>q_rank);-- output data
end structure;