Introduction

The objective of the note is to illustrate the problems that we met when we wanted to implement internal ram of Flex 10k (i.e. EABs). The LPM component -- LPM_RAM_DQ is used instead of csdpram (Cycle-Shared Dual-Port RAM).

Design

In our project, we plan to use internal ram to store and retrieve the data. These data include the histograms of the query image and the candidate image, the distance calculation results and rank calculation results. Each data width is 16 bits. Since there are 12kbits internal ram in FLEX10k and the total ram disk space, which we need, is no more than 2.5 kbits, 8 pieces of internal ram had originally been designed. But when we began to instantiate the first piece of ram for histogram of query image, the actual 768bits ram used up all 6 blocks of EABs (Figure 1 and query_rams.vhd). That means we couldn’t instantiate all pieces of ram in our design. We found that not only the capacity of ram will affect the usage percentage of EABs (as we usually think), but also the input and output IO pins, which means the wider the address and data width, or the more pieces of rams instances you use, the more EABs will be occupied.

Because that problem couldn’t be fixed, the histograms for the R, G and B components of the query image and the candidate image were combined together by increasing the address lines (Figure 2. and EAB_rams.vhd) from 4 to 6. This way we can decrease the ram pieces from 3 (one instance of ram for R, G and B in parallel) to 1 (one instance for R, G, B). Therefore, the total number of pieces of ram was reduced to 4, but they still didn’t fit.

Finally, by storing the images’ updated ranks in registers instead of in the internal ram, enough memory was made available for storing the histograms and distances. The 3 ram instances take all 6 full EAB blocks when only 48(words) ´ 16(bits) ´ 3 = 2304 bits are required (Figure 3 and EAB_rams.vhd).

Actually, in our final design, we end up by using only 2 pieces of internal ram for query image and candidate image and cut the distance ram off. The distance is calculated after we get the histogram of each new image and it is directly used to calculate and refresh the ranks so that we do not need to store the distances of each candidate images (EAB_rams1.vhd).

Although Altera recommends Cycle-Cycle Dual-Port RAM (csdram) to instantiate the internal ram for Flex10k family (from Altera website), we still got the foregoing problems when we use csdram modules (EAB_rams_1.vhd). Also, we find that even the percentage of used EABs decreases a little bit, but we pay the price of using some of the logic cells, which is not desirable. Another disadvantage of using csdram is that it is dual port ram, which makes the interface more complicated. We finally decided to use lpm_ram_dq instead of csdram.

Memory Initialization

If you want to initialize the internal ram only once, you can do it simply by adding the *mif or *.hex file (memory initialization file) into LPM RAM modules. However, if you want to initialize it several times, you have to create memory initialization VHDL file instead of *.mif file. That is what we learned from our project.

We tested all of the VHDL codes on Maxplus2 9.2.3 and 9.5version and got the same results.

If you have questions about it, feel free to contact with yuxin wang, yunan xiang.