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-- LCD control module 
-- Course       : EE 552
-- Project      : Wired CDMA
-- Author       : Jessamyn Smith
-- Student ID   : 0384675
-- Date         : November 11, 2000
-- File Name    : lcdcont.vhd
-- Architecture : Behavioural
-- Description  : This module provides control signals to the
--                LCD and instantiates a clock divider in
--                order to provide a working demonstration.
-------------------------------------------------------------



library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all;

entity lcdcont is
	generic ( asciiwidth : positive := 8);
	port (	clk : in std_logic;     -- 2.5 kHz
		reset : in std_logic;  -- assign to a pushbutton
		mode : in std_logic;  -- assign to a dip switch
                                      -- changing mode causes the
                                      -- display to change dynamically

	        increment : in std_logic;  -- assign to a pushbutton
                                           -- causes data in display to
                                           -- increment
			
		lcd_highbit: in std_logic;
			
		data_out : out std_logic_vector(asciiwidth-1 downto 0); -- lcd data   
	        rw_out : out std_logic;  -- lcd read(1)/write(0) line
		select_out : out std_logic;  -- lcd select (0=data, 1=instruction)
		enable_out : out std_logic);  -- lcd enable line - must be pulsed!
end lcdcont;

architecture structural of lcdcont is

component lcd
	port (	clk        : in std_logic;
		reset      : in std_logic;
		data_valid : in std_logic;  -- causes lcd to start new write cycle when high
		mode       : in std_logic;  -- changes characters on display
                
		inputdata  : in std_logic_vector(asciiwidth*2-1 downto 0);
                --provides dynamic input to lcd
			
		lcd_data   : out std_logic_vector(asciiwidth-1 downto 0);
		lcd_select : out std_logic;
		lcd_rw     : out std_logic;
		lcd_enable : out std_logic;
		done       : out std_logic);  -- set low during write cycle, high if ready for new data
end component;

component clockdiv
	port(
    	clockin : in std_logic;
    	clockout : out std_logic );
end component;

constant countwidth : positive := 4;

signal data_int : std_logic_vector(asciiwidth*2-1 downto 0);
signal count_data : std_logic_vector(countwidth-1 downto 0);
signal letter : std_logic_vector(countwidth-1 downto 0);
signal count : std_logic_vector(countwidth-1 downto 0);
signal valid_int, enable_int, reset_int, done_int, rw_int : std_logic;
signal small_clk : std_logic;

begin

enable_out <= enable_int;

letter <= count_data + '1';
data_int <= "0011" & count_data & "0100" & letter;

display : process(small_clk)
	begin
	if reset = '0' then
		count <= (others => '0');
		count_data <= (others => '0');
		valid_int <= '1';
	elsif rising_edge(small_clk) then
		if done_int = '1' and increment = '0' then
			valid_int <= '1';
			if count_data = "1001" then
				count_data <= (others => '0');
			else
				count_data <= count_data +'1';
			end if;
			count <= (others => '0');
		else
			valid_int <= '0';
		end if;
	end if;
end process;

mylcd : lcd port map(
	clk => small_clk,
	reset => reset,
	data_valid => valid_int,
	mode => mode,
	inputdata => data_int,
	lcd_data => data_out,
	lcd_select => select_out,
	lcd_rw => rw_out,
	lcd_enable => enable_int,
	done => done_int);

div : clockdiv port map(
	clockin => clk,
	clockout => small_clk);

end structural;