-------------------------------------------------------------
-- Clock Divider 
-- Course       : EE 552
-- Project      : Wired CDMA
-- Author       : Charlie McCarthy
-- Student ID   : 0262730
-- Date         : October 28, 2000
-- File Name    : clockdiv.vhd
-- Architecture : Behavioural
-- Description  : Divides a clock period by 10000.  For the UP1
--                board (25 MHz), this outputs a 2.5 kHz clock.
-------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;

entity clockdiv is
  port(
    clockin : in std_logic;
    clockout : out std_logic );
end clockdiv;

architecture behavioural of clockdiv is

signal clock_int : std_logic;

begin

clockout <= clock_int;

  count : process(clockin)
    constant MAX : integer := 5000;
    variable counter : integer range 0 to max;
  begin
    if rising_edge(clockin) then
      if counter = MAX then
        if clock_int = '0' then
        	clock_int <= '1';
        else
        	clock_int <= '0';
        end if;
        counter := 0;
      else
      	counter := counter + 1;
      end if;
    end if;
  end process count;
end behavioural;