Get Parallel Port Working under Windows NT
Chuping Liu, Julien Lamoureux, Yuxin Wang, Yunan Xiang
Abstract
In this application notes, a
really working parallel port programming approach under Windows NT is
introduced. A demo with C and VHDL source code is included to illustrate the
usage of parallel port driver from Scientific Software Tools, Inc. to communicate
with Altera FPGA UP1 Board.
Parallel
Port Driver
As we know, direct programming
on the I/O port under Windows NT is prohibited because of the system stability
protection mechanism in Windows NT's kernel. However, Windows NT workstation is
very popular in the public computer laboratories in campus. In the past years
many students had to write their own codes to run under DOS to program directly
to the parallel port, as found in the past application notes. A much easier
method was found by installing a new driver. Here the DriverLINX I/O port
driver, produced by Scientific Software Tools, Inc. will allow us to control
the parallel port directly under Windows NT. This driver is free and can be
downloaded from http://www.sstnet.com/.
This driver has to be installed by Administrator of the PC machine since this
driver will be loaded by NT as a device and the installation will copy one file
(DlportIO.sys) to the system directory.
Parallel
Port DLL Needed by Windows Programming
The DLPortIO driver provides
two ways to write your program: C++ (Microsoft Visual C++ 5.0 and above or
Inprise C++ Builder or Borland C++ for Windows) and Microsoft Visual Basic (5.0
and above). Indeed it can be used in your program under any environment
whenever it can call a DLL. As written in the README.txt file in the package,
it contains the following components:
The available functions for C++
programming can be found from the header file "DLPortIO.H". You can
also refer to the MSVC or VB examples included to investigate the details how
to call the functions in the DLL.
Interface
Example
In the following, an interface
example used to demonstrate communication between the personal computer and the
UP1 board for our project will be introduced. The interface requires control
logic on at both PC and FPGA ends. On the PC side, the driver mentioned above
is used to control the parallel port. On the FPGA side, a controller will take
over the management of the interface. The PC end sends a series number from
0-255 in a loop to the UP1 board through the parallel port. The received data
by UP1 board will be displayed on LEDs in HEX.
PC Side
Because information is sent
from the PC to the FPGA uni-directionally, the parallel port is implemented
using the SPP mode. To program the parallel port in SPP mode, three registers
are used. "The port base address (I/O Base) is used to write to the data
lines. The parallel port status register address is at the port base address
plus one and is used to read the status of the parallel port. This will allow
for reading the ACK signal coming from the UP1 board. The parallel port control
register is at the port base address plus two and is used to control the
parallel port. This will allow setting the TRANSFER and STROBE
signals"[1]. The parallel port SPP mode register definitions are as
follows:
|
Label |
Bit 7 |
Bit 6 |
Bit 5 |
Bit 4 |
Bit 3 |
Bit 2 |
Bit 1 |
Bit 0 |
|
Data |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
|
Status |
|
/Ack |
|
|
|
|
|
|
|
Control |
|
|
|
|
/TRANSFER |
|
|
/Strobe |
FPGA Side
"To interface a PC
parallel port to the FPGA we will use 14 pins of the UP1 FPGA. These pins
include 4 input control signals from PC and 1 output status signal back to PC.
In the 4 control signals, one for strobe, one for enable, one for data_status,
one for anImgEnd. The 1 status pin is for Ack. The left 8 pins for input data
lines.
The pin layout from the PC
parallel port is as follows:
|
Description |
Name |
Pin |
Type of Pin |
|
Strobe |
STROBE |
1 |
Output |
|
Acknowledge |
ACK |
10 |
Input |
|
Transfer data (start/stop) |
TRANSFER |
17 |
Output |
|
Data Bit 0-7 |
Data |
2 - 9 |
Output |
These pins will connect to the
UP1 FPGA as follows:
|
PC Parallel Port Pin Name |
UP1 FPGA Pin Name |
Type of Pin |
|
STROBE |
nStrobe |
Input |
|
ACK |
nAck_to_pc |
Output |
|
TRANSFER |
nEnable |
Input |
|
Data |
data_from_pc |
Input |
The 10 input lines will have to
be connected to the UP1 FPGA through 2 74LS245 buffers and the 1 output line
will have to be connected through another 74LS245 buffer. This will ensure that
the parallel port and FPGA do not damage one another" [1].
Here are the C code (handshake.cpp, handshake.h, Dlportio.h, Dlportio.lib) and
VHDL code (disp_parport_test.vhd, led_hex.vhd).
References
1. Rabi Mahapatra, Xilinx
Chapter 13 - Parallel Port I/O