MAX+plus II Annoyances

an application note by Stephen Tang of the Interactive Audio Manipulation Processor (iAMP) Team

Contents

• Welcome
• Compiler Issues
  • File Dependencies
  • Bugs in Older Versions of MAX+plus II
• VHDL Issues
  • Processes
    • redundant use of 'event
    • if statements versus case statements
  • Port Maps
• Some Other Resources

Welcome

The title of this app note is inspired by the book, Word 97 Annoyances, published by O'Reilly and Associates. This book describes how to get around many of the less attractive "features" of that ubiquitous word processor. I hope that, in some small way, I can do for MAX+plus II what ORA did for Word 97.

As you have no doubt discovered, MAX+plus II is not a very user-friendly program. Not only is the user interface admirably (?) archaic, but its grasp of VHDL sometimes seems wrong. And sometimes it really is wrong.

Complier Issues

I define a compiler issue as some problem that occurs during compilation but which is not directly related to your code.

File Dependencies

Let's say that you have a design file called foo.vhd that contains the following lines:

  library work;
  use work.FoobarPackage.all;

Let's also say that you have a package file called foopkg.vhd that ontains constant definitions and such but no architectures. foopkg.vhd looks like this:

  package FoobarPackage is
    various definitions here>
  end FoobarPackage

If you try to compile foo.vhd first, you will get this error message:

Library error: primary unit "FoobarPackage" denoted by prefix "WORK" must exist in the library

The solution is to compile foopkg.vhd first, then foo.vhd. Sometimes, however, this will not work either, and you may get this wonderful error:

Error: Unknown problem in c:\blah\foo.vhd (%DLS-E-BadCreSig, Unit DLS_STD:STANDARD.VHDLView creation date mismatch (newer) (used by unit DLS_MAXPLUS_PROJECT:FOOBARPACKAGE.VHDLView).)

Descriptive, isn't it? The online help for this message is no better. Near as I can figure, MAX+plus II throws this out when it has no clue about what's going on. This error can sometimes be solved by remembering to set the VHDL 1993 compiler option for ALL of your files.

It may also be possible to fix this problem by following the advice in the online help. Close MAX+plus II, delete all the .DLS files in the working directory, then restart MAX+plus II and try compiling again. Sometimes the file dependencies described in the .DLS files become unvalid and causes the compiler confusion.

Bugs in Older Versions of MAX+plus II

Sometimes you will get this "unknown problem error" regardless of anything that you do. In this case, try compiling your project using a newer version of MAX+plus II. I once got this error message while using Student Version 9.23 3/19/1999 on my home computer and could not find any way to get rid of it. In desperation, I tried compiling my files under Full Version 9.3 7/23/1999 on the Sun workstations in CEB 531. Lo and behold, the error magically disappeared. When I copied the compiler-generated files from the Sun filesystem to my home computer then tried again to compile with the Student Version of MAX+plus II, everything worked.

VHDL Issues

These are problems that are related to how MAX+plus II handles VHDL.

Processes

redundant use of 'event

Redundant use of the 'event signal attribute in a process can cause some cryptic errors. A specific example I encountered was caused by the following code:

  ActivateBasedOnState: process(CurrentState)
  begin
    if CurrentState'event then -- this line is bad
      case CurrentState is
        when ST_COUNTING =>
          led <= '0';
        when others =>
          led <= '1';
      end case;
    end if;                    -- this line also bad
  end process
  ActivateBasedOnState;

The if-statement in the process is really not necessary since the process is sensitive to transitions on the CurrentState signal. However, rather than ignoring it or flagging it as an error during compilation, MAX+plus II offers this message:

Error: Unknown problem in c:\somepath\somefile.vhd (%SynPrep-F-InternalError, Internal error: "Subtype node with constraint length not = 0 or 1" in eGetDiscreteRangeBounds at line 363 of file vhdlutil.c.)

This error message doesn't even indicate what line of your code caused the error. The nonobvious solution to this problem is to remove the two lines flagged as bad.

if statments versus case statements

Sometimes code that looks perfectly fine, logically, will give you an error. I surmise that this is because, despite it making logical sense, the code in question is not physically synthesizable. Consider the following example:

  MakeHSyncIntoClock: process(vga_h_sync)
  begin
    if vga_h_sync = TRUE then
      HSyncClock <= '1';
    else -- vga_h_sync = FALSE then
      HSyncClock <= '0';
    end if;
  end process MakeHSyncIntoClock;

This code will elicit the following error:

Error: Line ##: File c:\not\my\fault.vhd: Else Clause following a Clock edge must hold the state of signal "HSyncClock"

A simple workaround is to use a case statement instead of an if statement:

  MakeHSyncIntoClock: process(vga_h_sync)
  begin
    case vga_h_sync is
      when TRUE =>
        HSyncClock <= '1';
      when FALSE =>
        HSyncClock <= '0';
    end case;
  end process MakeHSyncIntoClock;

Problem solved.

Port Maps

It is not possible to map a fraction of an output standard logic vector to some signal. Let us say that you are using the following component and signal:

  component Blah
    port (
      clock: in std_logic;
      BlahOut: out std_logic_vector(MAX downto 0);
    );
  end component;
  
  signal Connector: std_logic_vector(MAX-1 downto 0);

If you try to create a port map like this:

  MyBlah: Blah port map (
    clock => clock,
    BlahOut(MAX-1 downto 0) => Connector
  );

you will get the following cryptic error message:

Error: Unknown problem in c:\blah\blah.vhd (%DLS-F-InvNode, Invalid node (signature = 18459); in GetAttr (qName).)

The solution is to redefine Connector (or use another signal) such that it has the same width as BlahOut.

Some Other Resources

Many students in the past have written their own app notes describing workarounds for MAX+plus II. Here are some handy links to those other documents so you won't have to go hunting around.

From Fall 1998:

Optimizing Techniques and Other Useful Tips by Patrick Chan et al.

Mr. Chan describes various ways to improve the synthesis of your code. He addresses case statements, clocking, process sensitivity lists, the "signal has no source" error, and use of the integer type.

From Winter 1998:

The Application Notes by the Car Park Group

Two relevant app notes are provided here. One talks about limitations in state machines and process sensitivity lists and the other provides tips on using the MAX+plus II waveform simulator.

ALTERA MAX+plus II INTRODUCTION by Mark Fedorak

While this document does not specifically address MAX+plus II bugs or quirks, it contains useful walkthoughs on the usage of various MAX+plus II features.

Altera Maxplus2 Bugs and Fixes by Rob Chapman

Mr. Chapman discusses two issues; negative number assignment in concurrent case statements, and non-zero indexed arrays across a port.

From Winter 1999:

Working WITH Altera's Maxplus2... by Andrew Dunmore and Anthony Eshpeter

These guys discuss problems with the lpm_shiftreg library, assigning values to generic maps, and creating multiple finite state machines in a single architecture.