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-- A  simple I/O port
-- Author       : Ralph Nevins
-- Student ID   : 395710
-- Date         : Mar. 2000
-- File Name    : port_a.vhd
-- Architecture : 
-- Description  :    port for the 6805
--                mangeled for no DDRA signals ;) 
-- Acknowledgements: Roth, Digital design using VHDL, appendix e
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library ieee;
use ieee.std_logic_1164.all;

entity PORT_A is
port(clk, rst_b, Port_Sel, ADDR0, R_W: in std_logic;
                DBUS_out:  out std_logic_vector(7 downto 0);
                DBUS_in:   in std_logic_vector(7 downto 0);
                PinA: out std_logic_vector(7 downto 0);
                PoutA: in std_logic_vector(7 downto 0));
end PORT_A;

architecture port1 of PORT_A is
signal PORTA : std_logic_vector(7 downto 0);
signal loadPORTA : std_logic;

begin                   

 loadPORTA <= '1' when (Port_Sel='1' and ADDR0='0' and R_W='1') else '0';
-- ReadPORTA <= '1' when (Port_Sel='1' and ADDR0='0' and R_W='0') else '0';


-- pin interface logic

  PinA <= PORTA ;
  DBUS_out <= PoutA  when (Port_Sel='1' and ADDR0='0' and R_W='0');  


process (clk)    -- this process writes to the port registers
begin
      wait until CLK'event and CLK='0';
    if (loadPORTA = '1') then 
	PORTA <= DBUS_in ;
    end if;
end process;
end port1;