-------------------------------------------------------------
-- A  6805 support circuit
-- Author       : Ralph Nevins
-- Student ID   : 395710
-- Date         : Mar. 2000
-- File Name    : m68hc05.vhd
-- Architecture : 
-- Description  :  memory mapping of i/o ram and rom support  
-- Acknowledgements:  Roth, Digital design using VHDL - chapter 11
-------------------------------------------------------------
library IEEE;
use  IEEE.STD_LOGIC_1164.all;
use  IEEE.STD_LOGIC_ARITH.all;
use  IEEE.STD_LOGIC_UNSIGNED.all;
LIBRARY lpm;			 -- required for the use of lpm functions 
USE lpm.lpm_components.ALL;

entity m68hc05 is
    port(clock, rst_b, irq, SCint : in std_logic;
	 PortAin, PortBin, PortCin : in std_logic_vector(7 downto 0);
	 PortAout, PortBout, PortCout : buffer std_logic_vector(7 downto 0);
	 addresses : buffer std_logic_vector(12 downto 0);
	 dbus_ram_lo_out: buffer std_logic_vector(7 downto 0);
	 wr,clk : buffer std_logic 
	 );
end m68hc05;

architecture M6805_64 of m68hc05 is
    
    component cpu6805
	port(clk, rst_b, IRQ, SCint: in std_logic;
	     dbus_out :out std_logic_vector(7 downto 0);
	     dbus_in : in std_logic_vector(7 downto 0);
	     abus : out std_logic_vector(12 downto 0);
	     wr: out std_logic);
    end component;

    component PORT_A
	port(clk, rst_b, Port_Sel, ADDR0, R_W : in std_logic;
	     dbus_out :out std_logic_vector(7 downto 0);
	     dbus_in : in std_logic_vector(7 downto 0);
	     PinA : out std_logic_vector(7 downto 0);
	     PoutA : in std_logic_vector(7 downto 0));
    end component;

    signal we, weRam, cs1, cs2,notclk,notwr,wrRam: std_logic;
    signal SelLowRam, SelHiRAM, SelPA, SelPB, SelPC, SelSC : std_logic;
    signal addr_bus: std_logic_vector(12 downto 0) := (others => '0');
    signal data_bus: std_logic_vector(7 downto 0) := (others => '0');

--    signal dbus_ram_lo_out, dbus_ram_hi_out: std_logic_vector(7 downto 0) := (others => '0');

    signal dbus_porta_out, dbus_portb_out, dbus_portc_out: std_logic_vector(7 downto 0) := (others => '0');
    signal dbus_rom_out: std_logic_vector(7 downto 0) := (others => '0');
    signal dbus_in, dbus_out: std_logic_vector(7 downto 0) := (others => '0');
    signal temp_vector: std_logic_vector(4 downto 0) := (others => '0');

    signal high: std_logic := '1';

begin

--     process (clock)
-- 	VARIABLE cnt    : INTEGER RANGE 0 TO 5;
--     BEGIN
-- 	IF (clock'EVENT AND clock = '1') THEN
-- 	    cnt := cnt + 1;
-- 	end if;
-- 	if (cnt > 2)  then
-- 	    clk <= '1' ;
-- 	else
-- 	    clk <= '0' ;   
-- 	end if;  
--     end process;
   clk <= clock;
    
    addresses <= addr_bus;

    CPU: cpu6805 port map (
	clk => clk,
	rst_b => rst_b,
	IRQ =>irq,
	SCint=> SCint,
	dbus_out =>dbus_out,
	dbus_in =>dbus_in,
	abus =>addr_bus,
	wr =>wr);

    PA: PORT_A port map (
	clk=>clk,
	rst_b=>rst_b,
	Port_Sel=>SelPA,
	ADDR0 =>addr_bus(0),
	R_W=>wr,
	dbus_out=>dbus_porta_out,
	dbus_in=>dbus_out,
	PinA => PortAout,
	PoutA => PortAin);
    PB: PORT_A port map (
	clk=>clk,
	rst_b=>rst_b,
	Port_Sel=>SelPB,
	ADDR0 =>addr_bus(0),
	R_W=>wr,
	dbus_out=>dbus_portb_out,
	dbus_in=>dbus_out,
	PinA => PortBout,
	PoutA => PortBin
	);
    PC: PORT_A port map (
	clk=>clk,
	rst_b=>rst_b,
	Port_Sel=>SelPC,
	ADDR0 =>addr_bus(0),
	R_W=>wr,
	dbus_out=>dbus_portc_out,
	dbus_in=>dbus_out,
	PinA => PortCout,
	PoutA => PortCin
	);

    notclk <= not clk ;
    wrRam <= wr and SelLowRam;
    weRam <= we and SelLowRam;

    tiny_ram_low    : lpm_ram_dq
	GENERIC MAP ( 
	    lpm_width           =>  8,		-- width of input and output data
	    lpm_widthad         =>  7,		-- width of address
--	    lpm_indata	  => "REGISTERED",	-- registered for synchronous use
--	    lpm_outdata	  => "REGISTERED",	-- registered for synchronous use
	    lpm_numwords        =>  128--,		-- maximum number of data
	    --lpm_address_control => "UNREGISTERED"
	    )
	PORT MAP (					--signals on the ports
	    data		=> dbus_out,	
	    we			=> wrRam,			-- determines write or read
	    address		=> addr_bus(6 downto 0),		-- address counter
	    inclock		=> weRam,		-- synchronized with system clock
	    outclock		=> cs1 , 
	    q			=> dbus_ram_lo_out);		-- output data


    local_rom : lpm_rom
	generic map  (
	    LPM_WIDTH =>8,
	    LPM_WIDTHAD     =>10,
	    LPM_file => "6805_test.mif" ,--,
	    LPM_ADDRESS_CONTROL => "UNREGISTERED",
	    LPM_OUTDATA => "UNREGISTERED"
	    )
	PORT map (
	    address	=>addr_bus(9 downto 0),
--	    inclock => clk,
--	    outclock=> clk,
	    q       => dbus_rom_out);


-- memory interface
    cs1 <= SelLowRam and not clk;   -- select ram on 2nd half of clock cycle
    cs2 <= SelHiRam and not clk; 
    we <= wr and not clk;           -- write enable on 2nd half of clock cycle

-- address decoder
    SelPA <= '1' when addr_bus(12 downto 1) = "000000000000" else '0';      
    SelPB <= '1' when addr_bus(12 downto 1) = "000000000001" else '0';
    SelPC <= '1' when addr_bus(12 downto 1) = "000000000010" else '0';

    SelLowRam <= '1' when addr_bus(12 downto 7) = "000001"  else '0';
--              32 <= addr <= 63
--    SelHiRam <= '1'  when addr_bus(12 downto 5) = "11111111" else '0';
    SelHiRam <= '0' ;--when addr_bus(12 downto 9) = "1111" else '0';
--              addr >= 8160 (1FE0h)
    temp_vector <=  SelHiRAM & SelLowRam & SelPC &SelPB & SelPA;
    with temp_vector select
	dbus_in <= 
--	dbus_ram_hi_out when "1000",
	dbus_ram_lo_out when "01000",
      	dbus_portb_out when "00100",
	dbus_portb_out when "00010",
	dbus_porta_out when "00001",
	dbus_rom_out when OTHERS;


end M6805_64;