The design  of the cpu core, and the I/O structure  were adapted from  ROTH,C. , Digital System Design using VHDL, 1997  .    The  code in Roth's book is not synthesizable using  Altera software, therefore significant structure modifications were made. The text is usefull to understand the functions of the processes within the cpu core.   Modifications to the shell (m68hc05) around the core were,  (1) to add  1k of ROM (adjustable) , (2) 128 bytes of RAM (adjustable) , and  (3) in this incarnation a third i/o port.   I/O port functionality was modified to remove the data direction register.   Thid design was tested & proved functional at 25.175/6 MHz, additional I/O or other modification may change the upper operating frequency. Commented code left in the vhdl files are part of testing or demonstrating previous (nonfunctional) code.

The assembler (PseudoSam 685 aka: 6805.zip ) used was pulled from the net  and is a "free to use for educational purposes" DOS based command line assembler.

Notes:

1. to simulate - modify the code segment  in m68hc05.vhd that controls the cpu clock to be  1 to 1, (extreemly useful for debugging instruction problems)
--     process (clock)
--      VARIABLE cnt    : INTEGER RANGE 0 TO 5;
--     BEGIN
--      IF (clock'EVENT AND clock = '1') THEN
--          cnt := cnt + 1;
--      end if;
--      if (cnt > 2)  then
--          clk <= '1' ;
--      else
--          clk <= '0' ;
--      end if;
--     end process;

 clk <= clock;
 

2. to synthesize- modify the code segment    in m68hc05.vhd that controls the cpu clock to be  6 to 3 ,
     process (clock)
      VARIABLE cnt    : INTEGER RANGE 0 TO 5;
     BEGIN
      IF (clock'EVENT AND clock = '1') THEN
          cnt := cnt + 1;
      end if;
      if (cnt > 2)  then
          clk <= '1' ;
      else
          clk <= '0' ;
      end if;
     end process;

-- clk <= clock;
 

3. to create your mif file ,
•  create  a asm program
•  run it through the assembler ,
• the output is  {name}.obj  which is a motorola hex s19 file
• edit the obj removing the header information up to & including the address, remove the last byte from each line (checksum)
• remove the last line (closeout)
• the remaining  bytes are the opcodes and irq vectors.
• copy the bytes into a exsiting mif file  to keep the previous structure intact
• include your mif file in the rom  generic statement  LPM_file => "6805_test.mif"
4. changing  the ram and rom sizes  in m68hc05
• the address width must be modified   lpm_widthad =>  7
• the number of words must be modified   lpm_numwords =>  128
• the address buss vector size must be modified   address => addr_bus(6 downto 0)
• the "chip select "must  conform to a non overlaping address space with the other devices   I.E. SelLowRam <= '1' when addr_bus(12 downto 7) = "000001"  else '0';
5. adding i/o in m68hc05
• if your i/o has input capabilities  - the input mux must be modified 
•     temp_vector <=  SelHiRAM & SelLowRam & SelPC & SelPB & SelPA;

  with temp_vector select
        dbus_in <=
        dbus_ram_lo_out when "01000",
        dbus_portb_out when "00100",
        dbus_portb_out when "00010",
        dbus_porta_out when "00001",
        dbus_rom_out when OTHERS;
 
• he "chip select" must  conform to a non overlaping address space with the other devices   I.E. SelPC <= '1' when addr_bus(12 downto 1) = "000000000010" else '0';
 

 

The FILES

vhdl
- cpu6805.vhd - - m68hc05.vhd - - port_a.vhd -

  sample asm and the resulting mif
- flex.asm - - 6805_test.mif -

the assembler
- 6805.zip -