Tips for EE552 project


1. Start early so that you can discover the unexpected problems earlier.

2. Choose a reasonably sized project. Don't be too aggressive.

3. The size of the student's account is limited. It is a good idea to sharing the disk space with your project members or using the unix Revision Control System "RCS". Here are some commands from the lab5 instruction:

(Locked your file)

% cd ~/ee552/project

% mkdir RCS

% ci -l myfile.vhd

(Unlocked your file)

% rcs -u myfile.vhd

% co -l1.1 myfile.vhd

4. Removing all the .cnf files while you are still run out of disk space.

5. Try to get familiarize with MAX+plusII program as soon as possible. Be sure that the compiler of the Mentor Graphics is not the same as MAX+plusII program. Do not try to write the VHDL codes in Mentor Graphics and then compiler them in MAX+plusII program. It results the "unknown problem" error message in the compiler.

6. Break down your project into subsystems. Do it one by one. If you are working on the interface module with a hardware (i.e. keypad or LCD), try to test it by doing simulation in the MAX+plusII first before you download it to broad. Also, you must test the subunit individually. Do not assume that it works and find out later on when you put your project together that the interface module causing you problems. Then, it is time consuming to debug.

7. If you are testing the interface unit on the student board, you should test the I/O pins on the board whether they are working or not. If the pins that you are using are not working, you reassign them in MAX+plus II.

8. If you are designing a state machine in the program, you can reduce the number of logic cells by simplifying the state machine. Also, you should not use the loop function in the state machine. It causes your program unstable. Your program cannot perform the expected result.

9. The asynchronized reset is better than the synchronized reset for the complicated state machine. The state machine advances to the next state in the clock edge. If the state machine's reset is also clock-edge sensitive; the reset function does not work properly. The whole state machine becomes unstable.

10. The student board has to be grounded all the time while you are testing the interface unit.

Last update : April 6, 2000
By Felica Cheng, Eric Cheung, Tim Golding, David Li and Wilson Kwan