SRAM Interfacing Basics

by
Eric Cheung, Felicia Cheng, David Li, Tin Wai Kwan

Introduction:

For some of the 552 projects, large amount of temporary data needs to be stored for calculations. Although the FLEX10K has a total of 12,288 total RAM bits, it may not be enough for those memory hungry projects. There are many types of RAM you can pick, most of the projects in this courses have used either SRAM or DRAM. The major difference between them is that DRAM requires peroidic refresh of the memory, which is more difficult to interface than SRAM which only requires a constant DC voltage to keep the data alive.

Choosing a SRAM:

Ask yourself a few questions before you order any parts:

What is the required capacity?
What is the data arrangment? ie) 128k x 16bits and 256k x 8bits both equals 2MB.
How many pins? (too many pins = too many headaches)
Operating voltage? (for the FPGA, 5V)
Access speed?
Price? (Morris Locker has some SRAM)

Background:

There are many kinds of SRAM available. The capacity ranges from a few hundred bytes to few megabytes, and also there are volatile and non-volatile types. Most SRAM available is volatile, meaning all data stored will be lost once power down. In this application notes, we will mainly discuss how to interface with a 128k x 16 bit (2MB) nonvolatile SRAM, part number DS1258Y, by Dallas Semiconductor. The interfacing procedure for a volatile and non-volatile one are generally the same.

Description

The first thing you need to is the data sheet on the sram provided by the manufacturer, which can either download it from their website or ask for one by mail. Then you should carefully read through it to ensure it is really what you want.
There will be a read cycle and a write cycle. Each cycle involves a number of steps that must be followed sequentially. All SRAM cycles should be very similar, here is a possible sequence:

Read Cycle

Assert Address to address bus
Assert Output Enable to active state
Read Data from data bus
Pull Output Enable back to inactive state

Figure 1. Read Cycle Finite State Machine

Write Cycle

Assert Address to address bus
Assert Write Enable to active state
Write Data to data bus
Pull Write Enable to inactive state

There could be slight differences between different type of SRAM and their timing requirements.

Figure 2. Write Cycle Finit State Machine

Code Sample

An interfacing code example can be found here specifically for the DS1258Y SRAM.