----------------
-- file control_write.vhd
----------------
-- this program will set the ADC sample every 122us, which means 8192 samples/sec
-- if you want to change the # of samples per sec, you have to change the constant
-- "num" in the ADC_pkg.vhd depending on the number clock period needed.
----------------

library ieee;
use ieee.std_logic_1164.all;

library work;
use work.ADC_pkg.all;

entity ADCcontroller is
	
	generic(datawidth: positive:= 8);
	port(
		clk,			-- FPGA clk
		rst, 			-- reset
		Din : in std_logic;	-- Din from ADC chip
		DataRdy: out std_logic;	-- DataRdy signal
		convst: out std_logic;	-- convst signal to ADC chip
		sclk: buffer std_logic;	-- sclk signal to ADC chip
		Dout: out std_logic_vector(datawidth-1 downto 0)	-- Data out
	);
end ADCcontroller;

architecture controller of ADCcontroller is

type state_type is (
					reset,
					ready,
					start_count,
					ack0
					);

signal state: state_type;

signal ack: std_logic; 
begin

setack: ADC 
	generic map (datawidth => 8)
	port map(
		clk => clk,
		Din => Din,
		rst => rst,
		ack => ack,
		DataRdy => DataRdy,
		convst => convst,
		sclk => sclk,
		Dout => Dout
		);
 
one_sample: process(clk) is

variable count : natural range 0 to num;

begin
  if rising_edge(clk) then
	if (rst = '0') then
		state <= reset;

	else
		case state is
			when reset =>
				state <= ready;

			when ready =>
				count:=0;
				state <= start_count;

			when start_count =>	  	
				count := count + 1;
				if count = (num/2) then
					state <= ack0;
				else 
					state <= start_count;
				end if;

			when ack0 =>
				count:= count +1;
				if count = num then
					state <= ready;
				else
					state <= ack0;
				end if;

		end case;
	end if;
  end if;
end process one_sample;

with state select
	ack  <= '1' when ready|start_count,
				'0' when others;
end controller;