---------------------------------------------
--Project Gump
--Marc Binette
--Ralph Nevins
--Lambert Lo
----------------------------------------------
--servo_controller_counter.vhd
--This is a 12 bit counter.
--Input=>clock(1bit)
--output=>overflow(1bit), count_out(12bits)
--  	  topfourbits(4bits)

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL; 
USE ieee.std_logic_unsigned.ALL; 

--entity declaration of the generic counter with
-- a default of 12 bits, It also has an overflow bit
--which goes high every time the counter turns over.
ENTITY servo_controller_counter IS
	GENERIC (countwidth : positive := 12);
	PORT(clock : IN std_logic;
		overflow : BUFFER std_logic;
		topfourbits: BUFFER std_logic_vector(3 DOWNTO 0);
		count_out : BUFFER std_logic_vector(countwidth-1 DOWNTO 0));
END servo_controller_counter;

--behavioural discription of the counter
ARCHITECTURE behavioural OF servo_controller_counter IS
BEGIN

topfourbits <= count_out(countwidth-1 DOWNTO countwidth-4);
--process waits for clock or reset
counter : PROCESS(clock) IS
BEGIN
	IF (clock'event AND clock = '1') THEN 
		count_out <= count_out + 1;
		--if the counter has turned over then overflow goes high
		--or else overflow is low.
		IF count_out = 0 THEN
			overflow <= '1';
		ELSE
			overflow <= '0';
		END IF;
	END IF;
	
END PROCESS counter;

END behavioural;