Mark Mielke

Kreshka Niehaus

Winter, 2000

This application note will attempt to describe, for initial information and overview knowledge purposes only, the operation and composition of a Successive Approximation ADC (Analog to Digital Converter). It is not meant to be a complete or entire reference for all kinds of Analog to Digital Converters. Instead, it is meant to serve as an overview for students attempting to use ADC’s in their EE 552 projects or other that perhaps have little or no knowledge of the composition and operation of an ADC (that is otherwise seen and used as a complete chip).

A Successive Approximation ADC is comprised of a number of parts including a sample/hold control circuit, a comparator, an SAR (Successive Approximation Register), a DAC (Digital to Analog Converter), and an output latch. One by one, these individual parts will be explained and then the whole operation will be summarized:

Sample/Hold Control Circuit:

This circuit serves as an interface between the ADC’s input or the input analog signal to be encoded and the rest of the ADC. The S/H (Sample/Hold) control circuit sustains a certain point of an input analog signal for a certain amount of time (i.e. necessary for the rest of the circuit to react on this value). The S/H circuit is typically a pair of voltage follower op-amps in an open-loop or closed-loop configuration linked by a switch (CMOS or MOSFET, etc) and a holding capacitor. It is regulated by its own specifications such as its acquisition time, droop rate, sample-to-hold settling time, and slew rate, just to name a few. There is a deeper subject matter here and it is only but introduced.

Comparator:

The comparator is essentially an operational amplifier or differential amplifier that compares two signals. The first of these is the S/H (Sample/Hold) circuit output, or the analog input after it has passed through the S/H control circuit. The second is the DAC output which is essentially the D/A conversion of the current digital output of the ADC (i.e. a feedback loop of the current output). If the comparator output is too high, this means that the current DAC output is too low. Vice versa, if the comparator output is too low, the current DAC output is too high.

Successive Approximation Register (SAR):

The SAR has three inputs and two outputs. The first of these inputs is a clock signal that will usually be an input pin to the ADC. This will determine the rate at which the ADC encodes the input analog signal. The next input is a “start conversion” signal from the S/H control circuit. This signal clears the SAR thus starting the encoding of a new signal. The third input is the output from the comparator. If this output is high (the DAC output is too low, as above), this tells the SAR to increase the digital number that it outputs. Vice versa, if this output is too low (the DAC output is too high, as above), this tells the SAR to decrease the digital number that it outputs. The two outputs are a digital output (whose number of bits depend on the specs of the ADC) and a “end of conversion” (EOC) output that is ‘true’ or ‘false’ and indicates whether the current digital output data is “data valid”. This is an overall output from the chip as well as an input to the output latch.

The sequence of successive approximation in the SAR occurs as follows:

§ T=0; clear all digital output bits, set EOC=’F’.

§ T=1; set the MSB to ‘1’. If this is too much, clear it; if too little, keep it.

§ T=2; set the next bit to ‘1’. If too much, clear it; if too little, keep it.

§ T=3 to N; continue as above until after LSB, then set EOC=’T’.

Digital to Analog Converter (DAC):

The DAC is part of the feedback loop inside the ADC. It converts the current digital output (output from SAR) to an analog signal to be used as the second input to the comparator (to be compared with the current analog input signal). A ladder configuration DAC works as follows:

Based upon a certain input reference voltage, this type of DAC is essentially achieving a set of binary weighted currents the come together into the summing junction of an op-amp. For example, if the MSB is logic ‘1’, then a switch (CMOS, MOSFET, etc.) is closed that allows a current “0.5*I” or “I/2” (ie. half the maximum possible current; as the MSB represents half of a total digital value) through to the summing junction. If the next most significant bit is logic ‘1’, then a current “0.25*I” or “I/4” is allowed through to the summing junction. Thus, for a 4-bit digital signal of ‘1001’, an current of I/2 + I/16 = 9/16*I would appear at the input to the op-amp, added to an offset of I/16 equals 5/8*I or 5/8* V_Ref. This makes sense as ‘1001’+’1’ is 5/8ths of ‘1111’+’1’ or the maximum total in this case.

Output Latch:

The output latch simply serves as an interface between the digital output from the SAR and the overall digital output of the ADC. If the EOC signal from the SAR is ‘true’, then the SAR digital output is relayed through the output latch as the ADC’s main output.

After examining all the comprising parts, one can see how the ADC comes together. An analog signal is imputed and compared with a D/A conversion of the current digital output. As the starting digital output will be zeros, this will be gradually increased by the SAR until the comparator tells the SAR that the input signal and analog conversion of the output signal match. At this point, the next sample of the analog signal will enter into the picture, the comparator will no longer detect a match, and the SAR will adjust the digital output until it matches the changed value of the analog input. The process then continually repeats itself.

Additional References as provided by Angela Antoniu:

Author: Haznedar, Haldun.

Title: Digital Microelectronics / Haldun Haznedar

Published: Redwood City, Calif. : Benjamin/Cummings Pub. Co., C1991.

Paging: xv, 624 p. : ill. ; 24 cm.

Subjects: Digital Electronics, Microelectronics

UA Cameron Flr2 SciTech

Call Number: TK 7868 D5 H423 1991 – c.1

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Author: Demler, Michael J.

Title: High-Speed Analog-to-Digital Conversion / Michael J. Demler

Published: San Diego : Academic press, c1991.

Paging: xiv, 218 p. : ill. ; 24 cm.

Subjects: Analog to Digital Converters

UA Cameron Flr2 SciTech

Call Number: TK 7887.6 D382 1991 – c.1

_____________________________________________________________________

Author: Plassche, Rudy J. van de.

Title: Integrated Analog –to-Digital and Digital-to-Analog Converters / by Rudy Van de Plassche.

Published: Boston : Kluwer Academic Publishers, c1994.

Paging: xliv, 501 p. ; 25 cm.

Series: Kluwer International Series in Engineering and Computer Science

Subjects: Digital to Analog Converters and Analog to Digital Converters

UA Cameron Flr2 SciTech

Call Number: TK 7887.6 P715 1994 – c.1