Design

The evalcs program is a small program that runs around until it finds the two part values that added upto the value that was input at the command line. Using this program eliminates the need for a user to manually figure it out or to run their old cscounter to determine the values that they need to implement the correct clock divider. This program takes the first command line parameter as a value that the user wants to find. After this value is found the program outputs the two parts in decimal and hexidecimal notation for the user to view.

Here is the c source code for the program to determine the two parts of a cscounter:

File: evalcs.c

Why evalcs and clock_divide?

I wrote evalcs when I was creating clock_divide and did not want to continually use max2win to determine the values of the two parts of a carry-save counter that I needed to use. The program made it easier in that all I needed to do was run the program with a command line parameter (the number I wanted) and it would spit out the two parts in decimal and hexidecimal format. I wanted to have it output in binary as well so that it would be easier to put into the code, but I was unable to find a formatter that would let me do this easily.

I wrote clock_divide when I determined that for our MP3 decoder chip that we needed to have a clock that was running at ~1MHz and that the chip also required that data was valid on the falling edge of the clock. Thus it became necessary to create a clock with rising and falling edges operating at ~1MHz periods respectively. Since for the MP3 decoder chip we need to use a shift register, the rising edge of the new clock would trigger the shifting of data out onto the MP3 chip's datain line and the falling edge of the clock would be used by the MP3 chip to latch in the data. The use of the carry-save counter seemed to be a more efficient use of the ALTERA chip, and the resulting increase in performance by using a carry-save counter in the clock_divider circuit was also impressive. This increase in performance would allow for higher throughput and a more accurate clock_divider circuit. In testing their was only about a 0.2% loss in the resulting divided clock. That is for a 10MHz clock being divided into a 1MHz clock, the true frequency of the output clock was 0.998MHz