| It seems that an ever increasing number of projects require an Analogue to Digital Converter (ADC). This is of course no surprise. Many projects are interfacing with the real world, which as far as we can tell is analogue. There are a number of student application notes dealing with how to set up an ADC, but the question still remains, how do you pick which ADC to use? |
There are a few main items to consider, before selecting which ADC
is best suited to your project.
Precision or resolution is the next consideration. How many bits of resolution will you require. When you are considering this, you must also keep in mind the size of the FPGA that you are interfacing with. Added resolution will not help if you cannot process it. (The ADC0809 has 8 bit resolution.[2]) When comparing the accuracy of different ADCs you need to look at the amount of error in the LSB. Different types of ADCs are better at producing more accurate results while others are faster, see Types below. (The ADC0809 has 0.75 accuracy in the LSB.[1]) There is an obvious trade-off between accuracy, and speed. It takes longer to do a more accurate conversion. When considering the speed of an ADC, you need to look at how long it takes to do a conversion, not the clock speed. That is because certain types of ADCs require multiple clock cycles to complete a single conversion. Consider how often you would require new data, and select an ADC accordingly. Also decide if speed is more important and accuracy and vice versa. Also consider how long your input signal will remain stable. ADCs require input to be stable the length of a conversion to be accurate. (The ADC0809 takes at least 100 us to complete a conversion. Some ADCs, e.g.. ADC10662 and ADC10664 , convert as fast as 0.36 us.[1]) The range of voltage over which the ADC is capable of doing conversions, essentially the positive reference voltage and the negative reference voltage levels. Voltage dividers can also be used to bring the input voltage within the range of the converter. (The ADC0809 has a range from -0.1V up to Vcc + 0.1 V. Where the maximum value for Vcc is 6.0V.[2]) Multiplexing; does your project require analog input from more than one source? If so consider multiplexing the data. It will save a lot of wiring and input pins on the FPGA. The drawback is that the interface becomes more complicated. Many ADCs are available with multiple channels. (The ADC0809 has 8 channels available[2]) Ease of use is also an important factor to consider. The less time you have to spend getting an ADC to work the more time you'll have to make your project do really cool things. The less control signals required to run the converter, the simpler the interface will be. Also if there are application notes and previously written code available it should be easier to use as well. (Student application notes are available on a couple of different chips. There are also manufacturer application notes, which tend to be more useful than just the data sheet. Picking a chip that has some application notes available will probably make things easier.) |
| There are many different types of ADCs common ones include:
Successive Approximation Registers (SAR)
/ Dual Slope are the most common general purpose ADCs. They
use a single comparator which means that for each bit of resolution it
requires one successive comparison; the result is stored in an on chip
register. The result is small size, not obvious on the circa 1980
ADC0809, and low power but the drawback is time. They are good for
medium high resolution (10 to 22 bits) at low speeds (100 samples per second
to 2 000 000 samples per second) [3].
The Sigma-Delta ADC uses oversampling to acheive higher accuracy than the SAR. This only works if the input signal remains doesn't change faster than the sampling rate. Ultimately the Sigma-Delta architechture is slower than the SAR but can achieve higher resolution (up to 24 bits) and accuracy [3]. Flash ADCs are 10 to 40 times faster than the fastest SAR. The trade off for high speed is low resolution (6 to 8 bits) and high power consumption. There are 2N-1 high speed comparators connected in parallel required for N bit resolution. This results in high input capacitance. As a result very low source impedance is required, because source impeadance affects settling times. A buffer is required to isolate source capacitance and resistance [3]. Obviously derived from Flash architecture, the Semi-Flash ADC was designed to address the issue of low resolution in Flash ADCs while still maintaining high speed conversions. Resolutions of 10 to 12 bits can be achieved by incorporating multiple steps of Flash Architecture [3]. |
| [1]
National Semiconductor - Product Selection Guide
[2] ADC0808/0809 Datasheet [3] Texas Instruments - Analog Applications |