Pin Number |
Label |
Input/Output |
Description |
Required |
Note: All control signals should have
a high voltage from Vcc - 1.5 to 15V and a low voltage from 1.5V to -0.3V. |
1 |
IN3 |
Input |
Analog data in. It is selected as channel 3 by the multiplexer. CBA
= 011. |
No, can tie to ground |
2 |
IN4 |
Input |
Analog data in. It is on channel 4 of the multiplexer. CBA = 100. |
No, can tie to ground |
3 |
IN5 |
Input |
Analog data on channel 5 of the multiplexer. CBA = 101. |
No, can tie to ground |
4 |
IN6 |
Input |
Analog data on channel 6 of the multiplexer. CBA = 110. |
No, can tie to ground |
5 |
IN7 |
Input |
Analog data on channel 7 of the multiplexer. CBA = 111. |
No, can tie to ground |
6 |
Start |
Input |
It is a control signal from the FPGA, which tells the converter when
to start a conversion. It is a pulse of at least 100ns in width. |
Yes |
7 |
EOC |
Output |
Signal from the ADC. It goes low when a conversion is started and high
at the end of a conversion. Users can look for a rising edge transition. |
Yes |
8 |
2-5 |
Output |
This is a bit of the digital converted output. Where 2-8
is the LSB and 2 -1 is the MSB. |
No |
9 |
Output Enable |
Input |
Control signal for FPGA that turns the output of the ADC on while high.
Useful for handshaking. |
No, can tie to Vcc. |
10 |
Clock |
Input |
Clock signal from FPGA. Max 1.2MHz. |
Yes |
11 |
Vcc |
Input |
Power to the chip. Range 4.5V to 6.0V DC. |
Yes |
12 |
VREF(+) |
Input |
Top rail of Reference voltage. The voltage level that, when received
as an input, will output "11111111" to the FPGA. Max Value Vcc + 0.1V |
Yes |
13 |
GND |
Input |
Ground. 0V |
Yes |
14 |
2-7 |
Output |
This is a bit of the digital converted output. Where 2-8
is the LSB and 2 -1 is the MSB. |
No |
15 |
2-6 |
Output |
This is a bit of the digital converted output. Where 2-8
is the LSB and 2 -1 is the MSB. |
No |
16 |
VREF(-) |
Input |
Bottom rail of Reference voltage. The voltage level that, when received
as an input, will output "00000000" to the FPGA. Min Value -0.1V |
Yes |
17 |
2-8 |
Output |
This is a bit of the digital converted output. 2-8 is the
LSB. |
No |
18 |
2-4 |
Output |
This is a bit of the digital converted output. Where 2-8
is the LSB and 2 -1 is the MSB. |
No |
19 |
2-3 |
Output |
This is a bit of the digital converted output. Where 2-8
is the LSB and 2 -1 is the MSB. |
No |
20 |
2-2 |
Output |
This is a bit of the digital converted output. Where 2-8
is the LSB and 2 -1 is the MSB. |
No |
21 |
2-1 |
Output |
This is a bit of the digital converted output. 2 -1 is the
MSB. |
No |
22 |
ALE |
Input |
Control signal from FPGA. This should be a pulse from the FPGA sent
when the address is ready to be loaded into the ADC. The minimum pulse
width is 100ns. It can be tied to the Start line if the clock is operated
under 500kHz. |
Yes |
23 |
ADD C |
Input |
Control signal from FPGA. This is an address select line for the multiplexer.
It is the MSB of the select lines. |
No, can tie to ground |
24 |
ADD B |
Input |
Control signal from FPGA. This is an address select line for the multiplexer.
It is the Second bit of the select lines. |
No, can tie to ground |
25 |
ADD A |
Input |
Control signal from FPGA. This is an address select line for the multiplexer.
It is the LSB of the select lines. |
No, can tie to ground |
26 |
IN0 |
Input |
Analog data on channel 0 of the multiplexer. CBA = 000. |
No, can tie to ground |
27 |
IN1 |
Input |
Analog data on channel 1 of the multiplexer. CBA = 001. |
No, can tie to ground |
28 |
IN2 |
Input |
Analog data on channel 2 of the multiplexer. CBA = 010. |
No, can tie to ground. |