|This set of student application notes is to be used to help the user interface an Analog to Digital Converter (ADC) with an FPGA. It is important to note that the ADC0808/ADC0809 ADC used was a Texas Instruments chip although the notes should work just as well with a National Semiconductor device. Be sure to consult the manufactures data-sheets for other chips. The ADC0808/ADC0809 is an 8 bit ADC that also contains an 8 channel multiplexer. The FPGA used in this case was the Altera 10k20RC240-4 that is found on the UP-1 boards used in the course. The purpose of this documentation is to first introduce users to the ADC0808/ADC0809, then to outline how to connect external circuitry to the ADC, and then describe how to interface the chip with the FPGA. For a quick reference refer to table 2.|
|Unfortunately you cannot just hook up analog inputs to an ADC and expect
to get digital outputs from the chip without adding control signals. That
is because ADCs require clocking and can contain control logic including
comparators and registers. The ADC0808/ADC0809 contains all of these and
also has a multiplexer. This means that in order to get it to work, there
is a total of seven control signals that must be sent from the FPGA. These
are the address lines, A, B, and C, Address Latch Enable (ALE), Clock,
Start, and Output Enable (OE). There is also one control signal which is
sent to the FPGA, it is the End of Conversion (EOC) signal. Table
2 provides a summary of all of the input and output to the chip. All
of the signals are explained below.
Address LinesBecause the chip has an 8 channel multiplexer there are three address select lines: A, B, and C. C is the most significant bit and A is the least . See table 1 for details.
|Selected Analog Channel||
ALEALE is required to load the selected address lines into the ADC. Once loaded the multiplexer sends the appropriate channel to the converter on the chip. The ALE should be pulsed for at least 100ns in order for the addresses to get loaded properly. As with all control signals it is required to have an input value of Vcc - 1.5 up to 15V for a high and 1.5V down to -0.3V for a low. The following control signals are used to control the conversion.
ClockThe clock signal is required to cycle through the comparator stages to do the conversion. There are 8, 8 clock cycle periods required in order to complete an entire conversion. This means that an entire conversion takes at least 64 clock cycles. (Up to 72 if the start signal is received in the middle of an 8 clock cycle period.) The clock should conform to the same range as all other control signals. The maximum frequence of the clock is 1.2MHz. The maximum clock frequency is affected by the source impedance of the analog inputs. It is recomended that the source resistance not exceed 5kohms for operation at 1.2MHz and 10komhs for operation at 640kHz. Note that when operating the ADC at 500kHz and below the ALE signal and the Start signal can be tied together. This is how the ADC is implemented in the VHDL code provided.
StartThe purpose of the start signal is two fold. On the rising edge of the pulse the internal registers are cleared and on the falling edge of the pulse the conversion is initiated. Like the ALE pulse the minimum pulse width is 100ns. The signal can be tie to the ALE signal when the clock frequency is below 500kHz. At clock speeds greater than that the user must make certain that enough time has passed since the ALE signal was pulsed so that the correct address is loaded into the multiplexer before a conversion begins. Note that it can take up to 2.5 microseconds for this to occur. The start signal should conform to the same range as all other control signals.
OEThe Output Enable signal causes the ADC to actually output the digital values on the output lines. The ADC stores the data in a tri-state output latch until the next conversion is started, but the data is only output when enabled. In this implementation the OE signal is pulsed high one clock cycle after the EOC signal goes high and remains high until the data is safely stored into the desired register in the FPGA. The OE signal should conform to the same range as all the other control signals.
EOCThe End of Conversion signal is sent to the FPGA from the ADC. The signal goes low once a conversion is initiated by the start signal and remains low until a conversion is complete.
|Note: All control signals should have a high voltage from Vcc - 1.5 to 15V and a low voltage from 1.5V to -0.3V.|
|1||IN3||Input||Analog data in. It is selected as channel 3 by the multiplexer. CBA = 011.||No, can tie to ground|
|2||IN4||Input||Analog data in. It is on channel 4 of the multiplexer. CBA = 100.||No, can tie to ground|
|3||IN5||Input||Analog data on channel 5 of the multiplexer. CBA = 101.||No, can tie to ground|
|4||IN6||Input||Analog data on channel 6 of the multiplexer. CBA = 110.||No, can tie to ground|
|5||IN7||Input||Analog data on channel 7 of the multiplexer. CBA = 111.||No, can tie to ground|
|6||Start||Input||It is a control signal from the FPGA, which tells the converter when to start a conversion. It is a pulse of at least 100ns in width.||Yes|
|7||EOC||Output||Signal from the ADC. It goes low when a conversion is started and high at the end of a conversion. Users can look for a rising edge transition.||Yes|
|8||2-5||Output||This is a bit of the digital converted output. Where 2-8 is the LSB and 2 -1 is the MSB.||No|
|9||Output Enable||Input||Control signal for FPGA that turns the output of the ADC on while high. Useful for handshaking.||No, can tie to Vcc.|
|10||Clock||Input||Clock signal from FPGA. Max 1.2MHz.||Yes|
|11||Vcc||Input||Power to the chip. Range 4.5V to 6.0V DC.||Yes|
|12||VREF(+)||Input||Top rail of Reference voltage. The voltage level that, when received as an input, will output "11111111" to the FPGA. Max Value Vcc + 0.1V||Yes|
|14||2-7||Output||This is a bit of the digital converted output. Where 2-8 is the LSB and 2 -1 is the MSB.||No|
|15||2-6||Output||This is a bit of the digital converted output. Where 2-8 is the LSB and 2 -1 is the MSB.||No|
|16||VREF(-)||Input||Bottom rail of Reference voltage. The voltage level that, when received as an input, will output "00000000" to the FPGA. Min Value -0.1V||Yes|
|17||2-8||Output||This is a bit of the digital converted output. 2-8 is the LSB.||No|
|18||2-4||Output||This is a bit of the digital converted output. Where 2-8 is the LSB and 2 -1 is the MSB.||No|
|19||2-3||Output||This is a bit of the digital converted output. Where 2-8 is the LSB and 2 -1 is the MSB.||No|
|20||2-2||Output||This is a bit of the digital converted output. Where 2-8 is the LSB and 2 -1 is the MSB.||No|
|21||2-1||Output||This is a bit of the digital converted output. 2 -1 is the MSB.||No|
|22||ALE||Input||Control signal from FPGA. This should be a pulse from the FPGA sent when the address is ready to be loaded into the ADC. The minimum pulse width is 100ns. It can be tied to the Start line if the clock is operated under 500kHz.||Yes|
|23||ADD C||Input||Control signal from FPGA. This is an address select line for the multiplexer. It is the MSB of the select lines.||No, can tie to ground|
|24||ADD B||Input||Control signal from FPGA. This is an address select line for the multiplexer. It is the Second bit of the select lines.||No, can tie to ground|
|25||ADD A||Input||Control signal from FPGA. This is an address select line for the multiplexer. It is the LSB of the select lines.||No, can tie to ground|
|26||IN0||Input||Analog data on channel 0 of the multiplexer. CBA = 000.||No, can tie to ground|
|27||IN1||Input||Analog data on channel 1 of the multiplexer. CBA = 001.||No, can tie to ground|
|28||IN2||Input||Analog data on channel 2 of the multiplexer. CBA = 010.||No, can tie to ground.|
|The ADC0808/0809 was designed for simple interface with analog inputs,
especially transducers. There are a couple of limitations that follow:
|So now "all" that remains is actually connecting the ADC to the FPGA
and getting the FPGA to control it. The source
code provided was used to control an ADC0809 where only 4 inputs were
used, therefore, ADD C is tied to ground and so are the unused inputs.
Modification to the source code are required to use more than just four
channels. The ADC0808/ADC0809 uses CMOS technology and can be connected
directly to the Altera 10k20.
Source codeThe source code consists of a few of files. The first is the ad_converter.vhd file which contains the package information of the ad_converter module as well as the VHDL code for interfacing with the ADC. The other files are enabled register, a register, and a multiplexer. You will need to compile en_register.vhd, which is used in the ad_converter. You will also need to download multiplex.vhd and nregister.vhd. Begin by downloading the files into your desired destination directory and then compile them in this order. First compile en_register.vhd and then the ad_converter.vhd module.