-- file:ph_det.vhd
------------------------------------------ 
-- detects the phase difference   
-- between two input frequencies. 
-- The design is From: B. Razavi,
-- "Monolithic phase locked loops and 
--  clock recovery circuits", IEEE press. 
--
-- 
-- By Ahmed Allam
-- November 1999.
-- University of Alberta, EE552.

--------------------------------------
-- Compiles  with no known 
-- errors.
---------------------------------------


library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 


entity ph_det is 
	port ( a,b : in std_logic;
           qa, qb: out std_logic
         );
end ph_det ; 

architecture archtry3 of ph_det is
signal set_high, qa_int, qb_int,res :std_logic;
 component d2 port 
          ( inpu_c, d_in,reset:in std_logic ;
            q_out  :buffer std_logic 
          ); 
 end component d2;       
             

begin 
			  
 set_high <= '1';
 
d0: d2 port map (
	inpu_c => a,
    reset => res,
	d_in   => set_high,
    q_out  => qa_int
    );
               
d1: d2 port map (
	inpu_c => b,
    reset => res,
	d_in   => set_high,
    q_out  => qb_int
    );

res <= qb_int and qa_int;

qa <= qa_int;
qb <= qb_int; 

end  archtry3;