The block diagram of a phase/frequency detector (PFD) is shown in Fig. 1 [1]. If the frequency of input A is less than that at input B, the PFD produces positive pulses at Qa, while Qb remains at zero. Conversely if the frequency at input B is higher than the frequency at input A, the PFD produces pulses at Qb and Qa remains at zero. If both frequencies are equal, then the circuit generates pulses at either Qa or Qb with a width equal to the phase difference between the two inputs.

The VHDL code the PFD is attached. The state diagram shown in Fig. 2 is used to implement the PFD [1]. The circuit can change state only on a rising edge of A or B signals. If the PFD is in state 0 , Qa= Qb = 0 , then a transition on A takes it to state I , where Qa = 1 , Qb = 0. The circuit remains in this state until a transition occurs on B, upon which the PFD returns to state 0.

A possible implementation of the PFD is shown in Fig. 3 [1]. The circuit consists of two edge-triggered resettable flip-flops with their D inputs connected to logical one. Signals A and B act as a clock inputs of a DFFa and DFFb., respectively. We note that if Qa = Qb= 0 , a transition on A causes Qa to go high. Subsequent transitions on A have no effect on Qa, and when B goes high, the AND gate activates the reset of both flip-flops. Thus Qa and Qb are simultaneously high for a duration given by the total delay through the and gate and the reset path of the flip fops.

[1] B.Razavi, "Phase locked loops and clock recovery circuits, theory and design," IEEE press.