----------------------------------------------------
--file: clk_divide.vhd
--
--Function: Clock divider circuit to divide down
--	    the 1MHz system clock
--
--
--
--Author: Andrew Sung
--Date: October 10, 1999
--
----------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity clk_divide is
	port
	( clock		: in 	std_logic;
	  resetn	: in	std_logic;
	  clk_500k 	: out	std_logic;	-- 500kHz clock
	  clk_15k625	: out  	std_logic	-- 15.625kHz clock
	);
	
end clk_divide;


architecture  divide_down of clk_divide is
	constant divider_value	: positive 	:= 6;

	signal	temp_count : std_logic_vector (divider_value-1 downto 0);

begin

	process (clock, resetn)
	begin	
	
		if resetn = '0' then	--asynchronous active low reset
	
			temp_count <= (others => '0');
		
		elsif (clock'EVENT and clock = '1') then
			
			temp_count <= temp_count + '1';--increment counter by 1

		end if;

	end process;

	clk_500k    <=	temp_count(0);	--output 500kHz
	clk_15k625  <= 	temp_count(5);	--output 15.625kHz

end divide_down;