-- clk_div.vhd
-- the file will provide a new clock frequecy (base on the internal clock)
--simulates without known bugs

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


--div_clk_by : the number you want to divide the clock by
--num_bits : the number of bits required to hold the size of the
--constant div_clk_by
entity clk_div is
  generic (div_clk_by: positive :=3;
           num_bits: positive :=2);
  port (in_clk, enable, reset: in std_logic; -- clock, enable, reset
        out_clk: out std_logic); -- new clock frequency
end clk_div;

architecture behaviour of clk_div is

-- counter 
signal count: std_logic_vector(num_bits-1 downto 0);

begin

-- create new clock frequency
count_clk :process(in_clk)
begin
  if reset = '1' then
    count <= (others => '0');
  elsif rising_edge(in_clk) then
    if enable = '1' then
      if count = (div_clk_by - 1) then
        count <= (others => '0');
        out_clk <= '1';
      else
        count <= count + 1;  
        out_clk <= '0';
      end if;
    end if;
  end if;
end process count_clk;

end behaviour;